M
Marek Ponca
Guest
hi,
is there some way how to define an initial value of an output in verilog
?
....something similar as initial value of a signal in VHDL:
a : std_logic := '1';
There is a need for mixed-signal simulation, to have defined digital
initial values before the simulation starts. It would help the analog
simulator
to define the initial conditions.
Thanks,
Marek
is there some way how to define an initial value of an output in verilog
?
....something similar as initial value of a signal in VHDL:
a : std_logic := '1';
There is a need for mixed-signal simulation, to have defined digital
initial values before the simulation starts. It would help the analog
simulator
to define the initial conditions.
Thanks,
Marek