Initial Value at start of process

[Roger Planger]

Hi

I have declared a Type with different states as you can see.

type STATE_TYPE is (IDLE, STLDA, STLDB, ADDS, FINISHS);

My question now is, how can I say my VHDL compiler that when he starts we
are in the IDLE State? Afterwards
it is easy to jump from one state to another.

Thanks for any hints

R

 

[Roger Planger]

Sorry for this stupid question, I figured it out in the meantime

Cheers

 

[valentin tihomirov]

Sorry for this stupid question, I figured it out in the meantime

Actually, it is not. Meantime I was sure that initialization during
declaration
signal STATE: TENUM := IDLE;

is intended for simulation while synthesis style must be:

process(CLK, RST)
if ASYNC_RST and RST = '1'
STATE <= IDLE;
else if Rising_Edge(CLK)
if not ASYNC_RST and RST = '1' then
STATE <= IDLE;

It turns out that the redundancy is needed as Xilinx FPGA loader will
initialize FFs to the values found in the declaration section.

 

[Roger Planger]

Hi

THanks for this hint, my problem is that I dont have a reset signal at the
moment. Therefore I want my State Machine to
be in the Idle state right from the beginning. It looks like that I have to
add this reset port to my IP

cheers

Roger

"valentin tihomirov" <spam@abelectron.com> wrote in message
news:2sgg4iF1k12raU1@uni-berlin.de...

Sorry for this stupid question, I figured it out in the meantime

Actually, it is not. Meantime I was sure that initialization during
declaration
signal STATE: TENUM := IDLE;

is intended for simulation while synthesis style must be:

process(CLK, RST)
if ASYNC_RST and RST = '1'
STATE <= IDLE;
else if Rising_Edge(CLK)
if not ASYNC_RST and RST = '1' then
STATE <= IDLE;

It turns out that the redundancy is needed as Xilinx FPGA loader will
initialize FFs to the values found in the declaration section.

 

[Pieter Hulshoff]

Roger Planger wrote:

THanks for this hint, my problem is that I dont have a reset signal at the
moment. Therefore I want my State Machine to
be in the Idle state right from the beginning. It looks like that I have
to add this reset port to my IP

I believe that within an FPGA you can make sure the design starts in a
defined state. For an ASIC however this is not possible. As such it is good
practice to place a reset within your design, and if I may be so bold:
please make it a synchronous reset i.s.o. an asynchronous one...

Regards,

Pieter Hulshoff