Initial statment and input signal correlation

I have one input signal in my module named as check,whose value is read
from a file and set in top module,then this signal is connected with
this port.
in module's initial statment i have check like
if(check==1)
$display("CHECK HIgH");
this statement is not been executed.
why so???
THanks in advance
Mamta

 

[Art Stamness]

whose value is read from a file and set in the top module

How is the value read from a file ? just a guess, but probably :
...
intial begin
$some_pli ( "foo.file", check ) ;
end

and then you checkt it at:

initial begin
if ( check==1 )
$display ("CHECK HIGH"):
end

Welcome to the wonderful world of the race condition! Verilog does not
guarantee the order of evaluation of different "initial" blocks ( or
any always block in the same time slice for that matter ).

You have some options options :

- [Not great] # delay the observer of the signal. That is :

initial begin
#1 ; // Waiting for assignment to happen
if ( check==1 ) $display ("blah blah");
end

( If you absolutely positively have to have the value compared at time
0, then you could use #0. This will delay the execution until the next
time slice, still at the same time 0. )

-Art