Inferring Xilinx BlockRAM FIFO

[Kevin Neilson]

The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any way to infer them? Probably not. They're not that useful otherwise, unless you want to instantiate the primitive (not really), use CoreGen (no), and simulate using a unisim (who's got the time?).

I always thought it'd be nice if Synplify could infer the Systemverilog push_front and pop_back queue commands as a FIFO and then use its own SynCore tool to make a FIFO from that. I might have to wait another 7-8 years for that one.

 

[Petter Gustad]

Kevin Neilson <kevin.neilson@xilinx.com> writes:

The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any
way to infer them? Probably not. They're not that useful otherwise,
unless you want to instantiate the primitive (not really), use CoreGen
(no), and simulate using a unisim (who's got the time?).

In Vivado you can script IP generation. You might be able to generate a
FIFO on the fly prior to the actual synthesis. Check the Vivado
documentation.

I always thought it'd be nice if Synplify could infer the

It might also be possible to script the Synplify SYNCore FIFO Wizard
from TCL even though I never tried.

Synplify Premier has support for DesignWare where you can "infer" (or
more like parametrized instantiation) complex components. However, I
don't know if the DW_fifo_2c_df will map into the Xilinx block-RAM
FIFO's.

Systemverilog push_front and pop_back queue commands as a FIFO and
then use its own SynCore tool to make a FIFO from that. I might have
to wait another 7-8 years for that one.

I guess most Synthesis tools would tell you that the queues are
only supported for simulation.

//Petter

--
..sig removed by request.

 

[maxascent]

The Xilinx built-in blockRAM FIFOs seem pretty nice, but is there any wa
t=
o infer them? Probably not. They're not that useful otherwise, unles
you=
want to instantiate the primitive (not really), use CoreGen (no), an
simu=
late using a unisim (who's got the time?).

I always thought it'd be nice if Synplify could infer the Systemverilo
pus=
h_front and pop_back queue commands as a FIFO and then use its own SynCor
=
tool to make a FIFO from that. I might have to wait another 7-8 years fo
=
that one.

Yes, just create your own FIFO in Verilog or VHDL. I have done this and XS
will create a BRAM FIFO for you.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

 

Jon,

Did the synthesis tool infer a BRAM addressed by your own index counters, or did it infer a FIFO hard macro, using the built-in address HW in the FIFO?

The OP was seeking the latter.

I have not seen any synthesis tools automatically employ built-in FIFO address HW for RTL-described indexing counters and full/empty logic.

Andy