Inferring RAM with FOR loop

Hi all,
I have written a simple code where data from a matrix(2-D array) is
Xored with single dimensional array.
On synthesis, things are being mapped in LUT's and Latch. I want to use
Block RAM's as in my case B-RAM's are sufficiently available on
VIRTEX-II FPGA device. I have read help of synplicity and XST and have
used ATTRIBUTE as told by them.

Synplicity and Xilinx guys are telling me that this cant be done in FOR
loop and are recommending to use a template. But this defeats the
flexibility of VHDL, as using templates is as good as doing schematic
entry.
I need coments from you experts.

---------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
package CONV is
constant N : integer := 16 ; -- number of elements to sort
constant M : integer := 8 ; -- size of word to sort

constant A : integer := 3 ; --counter_length = Length of Vector
Matrix = 2^A

type MATRIX is array (0 to (2**A)-1 , 0 to N-1) of std_logic ;

type HQARRAY is array (0 to N-1) of std_logic ;

end CONV;

----------------------------------------------------------------------
--- -------------------------------
--SIGNAL XORed_sig should become RAM.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.CONV.all;

entity XORblock is
port(
Reset : in STD_LOGIC;
clock : in STD_LOGIC;
WE : in STD_LOGIC;
HardQuantIN : in HQARRAY;
MatrixIN : in MATRIX ;
XORed_out : out MATRIX
);
end XORblock;

architecture archXORblock of XORblock is

signal XORed_sig : MATRIX ;
-------****Attribute for BLOCK RAM*****-----
attribute syn_ramstyle : string;
attribute syn_ramstyle of XORed_sig : signal is "block_ram";
--------------------------------------------

begin

XORingrocess (clock,Reset)

begin
if Rising_edge(clock) then
if Reset = '1' then
---Fill the Array with '0'
for l in 0 to M-1 loop
for m in 0 to N-1 loop

XORed_sig(l,m) <= '0';

end loop;
end loop;

for i in 0 to M-1 loop
for k in 0 to N-1 loop

XORed_sig(i,k) <= MatrixIN(i,k) xor HardQuantIN(k);

end loop;
end loop;
end if ;

if (we='1') then
XORed_out <= XORed_sig ;
end if;
end if;
end process XORing;

end archXORblock;

 

[Andy]

Two problems:

First, Rams are inferred from arrays of arrays, not 2-dimensional
arrays. You can also infer rams from arrays of integers, enums,
booleans, etc. You can even infer a single bit ram from a
std_logic_vector if the access conditions are right. Dual port rams
give you access to two addresses at a time (each clock cycle).

Second, you can only access one address of a single port ram in the
same clock cycle. You are trying to access every address in one cycle,
which forces the synthesis tool to infer registers. You need to set up
an address counter that steps through the addresses, and accesses only
one address on each clock.

Andy