Inferring parallel_add under quartus

Hello,

I would like that quartus auto inffer an parallel add...

I tried various code and it only inffer 2 adder...

I tried this :

process (RST,CLK)
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT <=SIGNED(A(7) & A);
B_INT <=SIGNED(B(7) & B);
A1 <= A_int + B_int;
A2 <= signed(A1(8) & a1);

C_INT <= signed(C(7) & C(7) & C);
ADD_OUT <= A2 + C_INT;
end if;
end process;

is there anybody who have also do this ?

thanks

 

[Andy Peters]

patrick.melet@dmradiocom.fr wrote:

Hello,

I would like that quartus auto inffer an parallel add...

I tried various code and it only inffer 2 adder...

I tried this :

process (RST,CLK)
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT <=SIGNED(A(7) & A);
B_INT <=SIGNED(B(7) & B);
A1 <= A_int + B_int;
A2 <= signed(A1(8) & a1);

C_INT <= signed(C(7) & C(7) & C);
ADD_OUT <= A2 + C_INT;
end if;
end process;

is there anybody who have also do this ?

your homework assignment: tell us why this doesn't work the way you
expect it should work ...

-a

 

[Ralf Hildebrandt]

Andy Peters wrote:

I tried various code and it only inffer 2 adder...

process (RST,CLK)
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT <=SIGNED(A(7) & A);
B_INT <=SIGNED(B(7) & B);
A1 <= A_int + B_int;
A2 <= signed(A1(8) & a1);

C_INT <= signed(C(7) & C(7) & C);
ADD_OUT <= A2 + C_INT;
end if;
end process;

is there anybody who have also do this ?

your homework assignment: tell us why this doesn't work the way you
expect it should work ...

Well ... we should give a hint:
Think about the die VHDL delta delay! What is the difference between a
variable and a signal?

Ralf

 

process (RST,CLK)
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT <=SIGNED(A(7) & A);
B_INT <=SIGNED(B(7) & B);
ADD_OUT <= A_int + B_int;
end if;
end process;


I would like that quartus inffer and parallele add....
When I wrote this code, it infer and simple adder and I would like to
inffer and adder with three or more input and I would like this adder
is a parallel adder like the paralle add in the megafunction wizard...

It's not an homework it's for my job because I have a design with a lot
of filter (matched filter, FIR filter, etc...) and I have a lot of
megafunction parallel add of different lenght (number of bits, number
of adder...)

So I would like to write a VHDL code which auto inffer the parallel add
I tried a lot of writing style and that only inffer simple adder...

I saw that the simple adder under quartus altera stratix have a 8 bit
output for two 8 bit input
and the parallel add have 9 bit ouptut for two 8 bit input...

So I tell you : is there anybody body wha have already do that...

 

patrick.melet@dmradiocom.fr wrote:

Hello,

I would like that quartus auto inffer an parallel add...

I tried various code and it only inffer 2 adder...

I tried this :

process (RST,CLK)
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT <=SIGNED(A(7) & A);
B_INT <=SIGNED(B(7) & B);
A1 <= A_int + B_int;
A2 <= signed(A1(8) & a1);

C_INT <= signed(C(7) & C(7) & C);
ADD_OUT <= A2 + C_INT;
end if;
end process;

is there anybody who have also do this ?

thanks

From Quartus II Development Software Handbook V5.0, chapter 6
"Recommended HDL Coding Styles". This handbook is free on the Altera

website.

Inferring Adder/Subtractors from HDL Code

To infer adder and subtractor functions, synthesis tools look for
adders and subtractors with the same set of inputs and outputs that are
multiplexed by a common signal. When the tool recognizes these
functions, Quartus II integrated synthesis merges the adders and
subtractors and converts them to an lpm_addsub megafunction, whereas
third-party synthesis tools typically use their own optimized logic.

To avoid verification mismatches, Quartus II integrated synthesis does
not infer lpm_addsub megafunctions when a third-party formal
verification tool is selected under EDA Tool Settings in the Settings
dialog box (Assignments menu).

The following code samples show Verilog HDL and VHDL examples of simple
adder and subtractors. The VHDL example includes a small userdefined
package to configure the widths. [I included only the VHDL
code--Charles]

VHDL Adder/Subtractor
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE my_package IS
CONSTANT ADDER_WIDTH: integer := 5;
CONSTANT RESULT_WIDTH: integer := 6;
SUBTYPE ADDER_VALUE IS integer RANGE 0 TO 2 ** ADDER_WIDTH - 1;
SUBTYPE RESULT_VALUE IS integer RANGE 0 TO 2 ** RESULT_WIDTH - 1;
END my_package;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.my_package.ALL;

ENTITY addsub IS
PORT (
a : IN ADDER_VALUE;
b : IN ADDER_VALUE;
addnsub : IN STD_LOGIC;
result : OUT RESULT_VALUE
);
END addsub;

ARCHITECTURE rtl OF addsub IS
BEGIN
PROCESS (a, b, addnsub)
BEGIN
IF (addnsub = '1') THEN
result <= a + b;
ELSE
result <= a - b;
END IF;
END PROCESS;
END rtl;

Hope this helps. My rule is that when I have a vendor-specific
question, I go first to the vendor's website.

Best regards,

Charles

 

Sorry, the first part of my post got cut off--probably my fault. The
reference is:

From Quartus II Development Software Handbook V5.0. Chapter 6
"Recommended HDL Coding Styles". This handbook is free on the Altera

website.

Charles

 

Yes I've got this recommended HDL Coding Styles but what you sent is
for inferring a simple adder or substractor but me I would like to
inffer a parallel adder, it's a megafunction from altera and it's an
adder with multiple inputs... it's what I need for the output of my
filters.. I don't want to put several adder it's simplier for me to
take advantage of the parallel_add...

Thanks...

 

[Ralf Hildebrandt]

patrick.melet@dmradiocom.fr wrote:

I gave you the hint about delta delays. Seems to be, that you did not
look into a VHDL book about this topic. So let's examine your code:

process (RST,CLK)
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT <=SIGNED(A(7) & A);

Ok - A_INT gets a new value in the NEXT delta delay!

B_INT <=SIGNED(B(7) & B);

The same here for B_INT.

ADD_OUT <= A_int + B_int;

And here you read A_INT and B_INT - but you read their values of the
ACTUAL delta delay. This means, you read the old value!

Let me add: VHDL is not case-sensitive, but you should avoind mixing
upper/lowercase.

end if;
end process;

In other words: What you have written is the following:
* 3 groups of flipflops: A_INT, B_INT and ADD_IUT
* all these flipflops are clocked synchronously with the same clock

=> If they are updated (clocked) synchronously and ADD_OUT is updated
with the value of A_INT and B_INT then the OLD values will be sampled.

Solution: Make A_INT and B_INT pure cominational logic.
Option 1): Put them outside the process
Option 2): Make them a variable (no delta delay - immediate update of
the value!)

process (RST,CLK)
variable A_INT, B_INT : signed(8 downto 0);
begin
if RST='1' then
ADD_OUT <= (others=>'0');
elsif CLK='1' and CLK'event then
A_INT :=SIGNED(A(7) & A);
B_INT :=SIGNED(B(7) & B);
ADD_OUT <= A_int + B_int;
end if;
end process;

I would like that quartus inffer and parallele add....

Well .. It think what you want is an adder plus a group of flipflops for
the result. ;-)

Ralf

 

Yes I'm totally agree with you. I have tested your code with variable
yet and that not implant the parallel_add, this parallel_add is a
special function under quartus and I think it's impossible to inffer it
directly in VHDL...
Your code inffer a simple adder...

I have tried with 3 inputs but it inffer 2 adder and not the
parallel_add it's very embarassing for me...

So I posted my question here in the aim to find someone who have do
that before me... but perhaps noone tried to inffer this parallel_add

So how do you do to add the output of a FIR filter ?

I've got a matched filter for CDMA communication with 63 taps (so an
adder with 63 input) and the paralle_add works fine and I don't have
problem in the timing : 110 MHz and I'm working at 88 MHz

 

[Ralf Hildebrandt]

patrick.melet@dmradiocom.fr wrote:

Yes I'm totally agree with you. I have tested your code with variable
yet and that not implant the parallel_add, this parallel_add is a
special function under quartus and I think it's impossible to inffer it
directly in VHDL...

I don't know exactly what you mean with "parallel_add". If it is a
macroblock provided by some library, then usually such a macroblock is
provided as a component, that has been instantiated inside your design.

Your code inffer a simple adder...

Yes - this is what I wanted to describe: a bit-parallel adder, which has
it's result stored in a group of flipflops.

What's wrong with inferring an adder this way? This is the usual way to
write target-independent code. Furthermore it depends of your synthesis
constraints, what type of adder will be inferred (carry-ribble adder
(area) or maybe CLA or something else (speed)). So this way is highly
flexible.

So how do you do to add the output of a FIR filter ?

Sorry, but I don't know what you are talking about.


Ralf

 

[Ralf Hildebrandt]

patrick.melet@dmradiocom.fr wrote:

I have studied that a FIR filter have taps delay and all the output of
the taps are multiplied by a coefficient and then all the output of the
multipliers are added !!!! isn't it ?
y=c(0).x+c(1).x(n-1)+...+c(N-1).x(n-N-1) with x the input and y
the output and c the coefficients so I can see that there are a lot of
adder !!!!

What the hell this has to do with you initial question?

You may implement a filter fully parallel (which results ins may
multipliers and adders) or sequentially (witch one adder and one
multiplier).

Ralf

 

I have studied that a FIR filter have taps delay and all the output of
the taps are multiplied by a coefficient and then all the output of the
multipliers are added !!!! isn't it ?
y=c(0).x+c(1).x(n-1)+...+c(N-1).x(n-N-1) with x the input and y
the output and c the coefficients so I can see that there are a lot of
adder !!!!