inferring latch

Guest
Hi,

when I wrote this :

INDICES : process (address_write)
begin
case address_write is
when "0101" =>
indice_freq(1) <= to_integer(unsigned(data_write));

when "0110" =>
indice_freq(2) <= to_integer(unsigned(data_write));

when "0111" =>
indice_freq(3) <= to_integer(unsigned(data_write));

when "1000" =>
indice_freq(4) <= to_integer(unsigned(data_write));

when "1001" =>
indice_freq(5) <= to_integer(unsigned(data_write));

when "1010" =>
indice_freq(6) <= to_integer(unsigned(data_write));

when others =>
indice_error <= '1';
end case;
end process INDICES;

Quartus synthesizer says me that it inffers latch for indice_freq !!!

how to do to not have latches ?

May I write this process with a CLOCK rising_edge ?

thanks
 
vhdldesigner.patrick@gmail.com wrote:

Quartus synthesizer says me that it inffers latch for indice_freq !!!
how to do to not have latches ?
May I write this process with a CLOCK rising_edge ?
Click to expand...
That would get rid of the latches,
but would retain the feature
of holding all of the old values.

Is that what you want?

-- Mike Treseler

thanks
Click to expand...
 
Quartus synthesizer says me that it inffers latch for indice_freq !!!
Yes and it is correct.
Click to expand...

When you assign to one element of your array such
as: indice_freq(1), what happens to the other elements?
They don't get updated, hence, they maintain (or store) their
value which results in a latch (because it is level sensitive
since there is no clock).

Latch Rule:
Latches occur in a combinational logic process any time a signal
is assigned a value and it does not get a value in all hardware
executions of the process.

how to do to not have latches ?
Make sure that for all executions of the process that all elements
Click to expand...
of indice_freq get a value. You can do this by adding the following
before your case statement (see the code below if you are not
sure where to add it):

indice_freq <= "000000" ; -- assuming 6 elements

Alternately,
indice_freq <= (others => '0') ; -- see array aggregates in your book

May I write this process with a CLOCK rising_edge ?
Yes if you want registers on the outputs.
Click to expand...
No otherwise.


INDICES : process (address_write)
begin
indice_freq <= "000000" ; -- assuming 6 elements
case address_write is
when "0101" =
indice_freq(1) <= to_integer(unsigned(data_write));

when "0110" =
indice_freq(2) <= to_integer(unsigned(data_write));

when "0111" =
indice_freq(3) <= to_integer(unsigned(data_write));

when "1000" =
indice_freq(4) <= to_integer(unsigned(data_write));

when "1001" =
indice_freq(5) <= to_integer(unsigned(data_write));

when "1010" =
indice_freq(6) <= to_integer(unsigned(data_write));

when others =
indice_error <= '1';
end case;
end process INDICES;

Cheers,
Click to expand...
Jim
SynthWorks VHDL Training
 
Using clocked processes instead of combinatorial ones eliminates the
possibility of inferring a latch.

Other fixes mentioned above will also work.

Whenever I see a case statement with a bunch of numeric target
expressions, I think "could this be done either in a loop, or directly
via indexing instead?" If the case (and any index conversion) may
result in indices outside the range of the array, use a loop,
otherwise, convert the expression directly to the index.

for i in indice_freq'range loop
if i + 4 = to_integer(unsigned(addr_write)) then
indice_freq(i) <= to_integer(unsigned(data_write));
exit; -- optional
end if;
end loop;

Since loops are unrolled in synthesis, the value of i is essentially
static for their purposes, which means that i+4 is also static, and is
not computed in hardware.

Andy

On Apr 13, 10:07 am, Jim Lewis <j...@synthworks.com> wrote:
Quartus synthesizer says me that it inffers latch for indice_freq !!!
Yes and it is correct.

When you assign to one element of your array such
as: indice_freq(1), what happens to the other elements?
They don't get updated, hence, they maintain (or store) their
value which results in a latch (because it is level sensitive
since there is no clock).

Latch Rule:
Latches occur in a combinational logic process any time a signal
is assigned a value and it does not get a value in all hardware
executions of the process.

how to do to not have latches ?
Make sure that for all executions of the process that all elements
of indice_freq get a value. You can do this by adding the following
before your case statement (see the code below if you are not
sure where to add it):

indice_freq <= "000000" ; -- assuming 6 elements

Alternately,
indice_freq <= (others => '0') ; -- see array aggregates in your book

May I write this process with a CLOCK rising_edge ?
Yes if you want registers on the outputs.
No otherwise.

INDICES : process (address_write)
begin

indice_freq <= "000000" ; -- assuming 6 elements

case address_write is
when "0101" =
indice_freq(1) <= to_integer(unsigned(data_write));

when "0110" =
indice_freq(2) <= to_integer(unsigned(data_write));

when "0111" =
indice_freq(3) <= to_integer(unsigned(data_write));

when "1000" =
indice_freq(4) <= to_integer(unsigned(data_write));

when "1001" =
indice_freq(5) <= to_integer(unsigned(data_write));

when "1010" =
indice_freq(6) <= to_integer(unsigned(data_write));

when others =
indice_error <= '1';
end case;
end process INDICES;

Cheers,
Jim
SynthWorks VHDL Training
Click to expand...
 
On Apr 16, 7:56 am, "Andy" <jonesa...@comcast.net> wrote:
Using clocked processes instead of combinatorial ones eliminates the
possibility of inferring a latch.

Other fixes mentioned above will also work.

Whenever I see a case statement with a bunch of numeric target
expressions, I think "could this be done either in a loop, or directly
via indexing instead?" If the case (and any index conversion) may
result in indices outside the range of the array, use a loop,
otherwise, convert the expression directly to the index.

for i in indice_freq'range loop
if i + 4 = to_integer(unsigned(addr_write)) then
indice_freq(i) <= to_integer(unsigned(data_write));
exit; -- optional
end if;
end loop;

Since loops are unrolled in synthesis, the value of i is essentially
static for their purposes, which means that i+4 is also static, and is
not computed in hardware.

Andy

On Apr 13, 10:07 am, Jim Lewis <j...@synthworks.com> wrote:

Quartus synthesizer says me that it inffers latch for indice_freq !!!
Yes and it is correct.

When you assign to one element of your array such
as: indice_freq(1), what happens to the other elements?
They don't get updated, hence, they maintain (or store) their
value which results in a latch (because it is level sensitive
since there is no clock).

Latch Rule:
Latches occur in a combinational logic process any time a signal
is assigned a value and it does not get a value in all hardware
executions of the process.

how to do to not have latches ?
Make sure that for all executions of the process that all elements
of indice_freq get a value. You can do this by adding the following
before your case statement (see the code below if you are not
sure where to add it):

indice_freq <= "000000" ; -- assuming 6 elements

Alternately,
indice_freq <= (others => '0') ; -- see array aggregates in your book

May I write this process with a CLOCK rising_edge ?
Yes if you want registers on the outputs.
No otherwise.

INDICES : process (address_write)
begin

indice_freq <= "000000" ; -- assuming 6 elements

case address_write is
when "0101" =
indice_freq(1) <= to_integer(unsigned(data_write));

when "0110" =
indice_freq(2) <= to_integer(unsigned(data_write));

when "0111" =
indice_freq(3) <= to_integer(unsigned(data_write));

when "1000" =
indice_freq(4) <= to_integer(unsigned(data_write));

when "1001" =
indice_freq(5) <= to_integer(unsigned(data_write));

when "1010" =
indice_freq(6) <= to_integer(unsigned(data_write));

when others =
indice_error <= '1';
end case;
end process INDICES;

Cheers,
Jim
SynthWorks VHDL Training
Click to expand...
Oops, I left out indice_error...

inidce_error <= '1'; -- default
for i in indice_freq'range loop
if i + 4 = to_integer(unsigned(addr_write)) then
indice_freq(i) <= to_integer(unsigned(data_write));
indice_error <= '0';
exit; -- optional
end if;
end loop;

Andy
 
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