Inferring F7 / F8 Mux in Xilinx

[Kevin Neilson]

I'm posting this here for my own future reference.

If you infer a mux with fewer than 2**n inputs, Vivado won't infer the F7 or F8 muxes. Here is the trick to make sure you get the best synthesis.

Example, 5-input mux:

wire [7:0] mux_inputs[0:4]; // only 5 inputs
wire [7:0] mux_out;
wire [2:0] mux_sel;

always@(posedge clk)
if (mux_sel<5)
mux_out <= mux_inputs[mux_sel];
else
mux_out <= 'bx; // assign rest of 2**3-5 inputs to don't-care


Keywords: f7, f8, multiplexer, Vivado

 

[Kevin Neilson]

Here's an addendum. The style above only works for a 7-input mux, not a 5-input. For less than 7 inputs, Vivado still omits the F7. Here's the Vivado kludge:

wire [7:0] mux_inputs[0:4]; // only 5 inputs
wire [7:0] mux_out;
wire [2:0] mux_sel;
(*keep="true"*) wire [2:0] dummy_x[5:7];

assign dummy_x[5] = 3'bx;
assign dummy_x[6] = 3'bx;
assign dummy_x[7] = 3'bx;

always@(posedge clk)
if (mux_sel<5)
mux_out <= mux_inputs[mux_sel];
else
mux_out <= dummy_x[mux_sel];

After synthesis, Vivado uses extra LUTs to implement the KEEP dummy wires, but then it removes these in PAR.

This whole thing is ridiculous, but this is how you get Vivado to do what it's supposed to do.

 

[Kevin Neilson]

Nah, that doesn't always work either. This seems to work more consistently:

(*keep="true"*) wire [7:0] mux_inputs[0:7]; // only 5 inputs used
wire [7:0] mux_out;
wire [2:0] mux_sel;

// Assign unused mux inputs to 'bx so there are exactly 2^n inputs
assign mux_inputs[5] = 'bx;
assign mux_inputs[6] = 'bx;
assign mux_inputs[7] = 'bx;

always@(posedge clk)
mux_out <= mux_inputs[mux_sel];