Inferring dual port two output sram

  • Thread starter daniel.larkin@gmail.com
  • Start date
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daniel.larkin@gmail.com

Guest
Hi,

I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware). The following
code in ISE results in 2 dual port memories with a single input and
output - which is not what I want

always @(posedge clk)
begin
if (wr_en)
ram[waddr] <= data_in;
end
//-----------------------------------------------------------------------

always @(posedge clk)
begin
if(rst_n ==1'b0)
begin
data_out0 <= 'b0;
data_out1 <= 'b0;
end
else
if(wr_en!=1'b1)
begin
data_out0 <= ram[raddr0];
data_out1 <= ram[raddr1];
end
end

Any suggestions would be most welcome!
thanks
 
daniel.larkin@gmail.com wrote:
Hi,

I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware). The following
code in ISE results in 2 dual port memories with a single input and
output - which is not what I want

always @(posedge clk)
begin
if (wr_en)
ram[waddr] <= data_in;
end
//-----------------------------------------------------------------------

always @(posedge clk)
begin
if(rst_n ==1'b0)
begin
data_out0 <= 'b0;
data_out1 <= 'b0;
end
else
if(wr_en!=1'b1)
begin
data_out0 <= ram[raddr0];
data_out1 <= ram[raddr1];
end
end

Any suggestions would be most welcome!
thanks
Click to expand...
To end up with one dual-port memory, one of the outputs
in the second process needs to use the same address
as the write section, i.e. replace either raddr0 or raddr1
with waddr. Otherwise this can't be implemented in a
single DP RAM. What you've described is a quasi three
port memory (1 write and 2 read) since you have three
address buses.

Regards,
Gabor
 
For a dual port memory in the Xilinx architecture, each port has one
address, not two addresses. You specify a waddr which is different than
raddr0 and raddr1. You're describing a three port memory. If you can
use a 2x clock for the memory, it's simple to enable the write on the
equivalent of the 1x clock rising edge and the read on the 1x clk
falling edge by delivering the 2x clk with the write enable in the
correct place. The address also needs to be muxed but muxes are fast.


daniel.larkin@gmail.com wrote:
Hi,

I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware). The following
code in ISE results in 2 dual port memories with a single input and
output - which is not what I want

always @(posedge clk)
begin
if (wr_en)
ram[waddr] <= data_in;
end
//-----------------------------------------------------------------------

always @(posedge clk)
begin
if(rst_n ==1'b0)
begin
data_out0 <= 'b0;
data_out1 <= 'b0;
end
else
if(wr_en!=1'b1)
begin
data_out0 <= ram[raddr0];
data_out1 <= ram[raddr1];
end
end

Any suggestions would be most welcome!
thanks
Click to expand...
 
Sorry, it's early... I see now you don't need the read value during the
write. Define a wire for one of the addresses that looks like
rwaddr = wr_en? waddr : raddr0;
and use the rwaddr in both the write and appropriate read.


daniel.larkin@gmail.com wrote:
Hi,

I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware). The following
code in ISE results in 2 dual port memories with a single input and
output - which is not what I want

always @(posedge clk)
begin
if (wr_en)
ram[waddr] <= data_in;
end
//-----------------------------------------------------------------------

always @(posedge clk)
begin
if(rst_n ==1'b0)
begin
data_out0 <= 'b0;
data_out1 <= 'b0;
end
else
if(wr_en!=1'b1)
begin
data_out0 <= ram[raddr0];
data_out1 <= ram[raddr1];
end
end

Any suggestions would be most welcome!
thanks
Click to expand...
 
On 15 Aug 2006 01:20:34 -0700, "daniel.larkin@gmail.com"
<daniel.larkin@gmail.com> wrote:

Hi,

I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware).
Click to expand...
I haven't used Designware recently but I'd be very surprised if they
added memory inferring to its features. In ASICs one needs to run a
memory compiler which is specific to each process and it's supplied by
the library vendor (or another third party memory IP vendor). So you
probably will have to run a memory compiler get a model and
instantiate that model in your design. If so it makes more sense to do
the same for the FPGA flow too.
 
Thanks for that John! that definitely points me in the right direction

John_H wrote:
Sorry, it's early... I see now you don't need the read value during the
write. Define a wire for one of the addresses that looks like
rwaddr = wr_en? waddr : raddr0;
and use the rwaddr in both the write and appropriate read.


daniel.larkin@gmail.com wrote:
Hi,

I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware). The following
code in ISE results in 2 dual port memories with a single input and
output - which is not what I want

always @(posedge clk)
begin
if (wr_en)
ram[waddr] <= data_in;
end
//-----------------------------------------------------------------------

always @(posedge clk)
begin
if(rst_n ==1'b0)
begin
data_out0 <= 'b0;
data_out1 <= 'b0;
end
else
if(wr_en!=1'b1)
begin
data_out0 <= ram[raddr0];
data_out1 <= ram[raddr1];
end
end

Any suggestions would be most welcome!
thanks
Click to expand...
 
I wish to infer a dual port SRAM with one input write data port and two
output read data ports. Ideally I'd like describe this abstractly
enough so that the code will generate the correct hardware for my
prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
library (memory to be inferred via Synopsys Designware).

I haven't used Designware recently but I'd be very surprised if they
added memory inferring to its features. In ASICs one needs to run a
memory compiler which is specific to each process and it's supplied by
the library vendor (or another third party memory IP vendor). So you
probably will have to run a memory compiler get a model and
instantiate that model in your design. If so it makes more sense to do
the same for the FPGA flow too.
Click to expand...
aha :-( thanks for clearing that up.
 
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