Inferring a pipelined multiplexer

U

Uwe Bonnes

Guest
Hallo,

for one design I have 64 8 bit counters, where I need to read out one
counter pointed to by input 'sel' to output 'data'. Multiplexing should be
down in a two stage process, first 8 pieces 8-bit 8-to-1 multiplexer and in
the second stage a single 8-bit 8-to-1 multiplexer. The module boils down
to:

module pipeline_mux
#(parameter N_BITS = 6,N_CHANNEL = 64)
(
input clk,
input [ N_CHANNEL -1:0] cnt,
input [ N_BITS -1 :0 ] sel,
output reg [N_BITS -1+2 :0 ] data
);
reg [N_BITS-1+2:0] counter[0:N_CHANNEL-1];
reg [N_BITS-1+2:0] counter_p[0:7];
reg [ N_BITS -3 :0 ] j;
integer i;

always @(posedge clk)
begin
for (i=0; i<N_CHANNEL; i = i+1)
if(cnt)
counter <= counter + 1'b1;
/* First stage pileline */
for (j=0; j<8; j = j+1)
counter_p[j]<= counter[{sel[N_BITS-1:3], j[2:0]}];
/* Second stage pileline */
data <= counter_p[sel[2:0]];
end
endmodule // pipeline_mux

Simulation shows expected behaviour. Running with ISE 9.1 however HDL
synthesis reports:
....
Found 8-bit 64-to-1 multiplexer for signal <$varindex0000> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0001> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0002> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0003> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0004> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0005> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0006> created at line 55.
Found 8-bit 64-to-1 multiplexer for signal <$varindex0007> created at line 55.
....
Found 8-bit 8-to-1 multiplexer for signal <data$varindex0000> created at line 56.
....

8 64-to-1 multiplexers are inferred, despite the 8-to-1 multiplexers I hoped for

Later Low Level synthesis reports lots of unconnected nodes, where probably
the 64-to-1 multiplexers get pruned to 8-to-1.

Is there a better way to code the problem?

Thanks

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:
Hallo,

for one design I have 64 8 bit counters, where I need to read out one
counter pointed to by input 'sel' to output 'data'. Multiplexing should be
down in a two stage process, first 8 pieces 8-bit 8-to-1 multiplexer and in
the second stage a single 8-bit 8-to-1 multiplexer. The module boils down
to:
....
Click to expand...
to partially answer my own question:
The unconnected nodes were caused by the mismatch in width of the counters
and data .

Coding
for (j=0; j<8; j = j+1)
case (sel[N_BITS-1:3])
3'h0: counter_p[j]<= counter[{3'h0, j[2:0]}];
3'h1: counter_p[j]<= counter[{3'h1, j[2:0]}];
3'h2: counter_p[j]<= counter[{3'h2, j[2:0]}];
3'h3: counter_p[j]<= counter[{3'h3, j[2:0]}];
3'h4: counter_p[j]<= counter[{3'h4, j[2:0]}];
3'h5: counter_p[j]<= counter[{3'h5, j[2:0]}];
3'h6: counter_p[j]<= counter[{3'h6, j[2:0]}];
3'h7: counter_p[j]<= counter[{3'h7, j[2:0]}];
endcase // case (sel[N_BITS-1:3])

makes the HDL analysis infer the 8 8-to-1 multiplexes as expected. Is the
HDL analysis at fault or my coding style?

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Uwe Bonnes wrote:

Hallo,

for one design I have 64 8 bit counters, where I need to read out one
counter pointed to by input 'sel' to output 'data'. Multiplexing should be
down in a two stage process, first 8 pieces 8-bit 8-to-1 multiplexer and in
the second stage a single 8-bit 8-to-1 multiplexer. The module boils down
to:
Click to expand...
(snip)

If you want to pipeline it you will need a register in between.

Otherwise it is up to the synthesis software to find the best logic,
which may be a 64 to 1 multiplexer. If you put a register in between,
that should fix it.

-- glen
 
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
....
(snip)

If you want to pipeline it you will need a register in between.
Click to expand...
Isn't counter_p[] the register in between?

Otherwise it is up to the synthesis software to find the best logic,
which may be a 64 to 1 multiplexer. If you put a register in between,
that should fix it.
Click to expand...
I still wonder where the difference between
for (j=0; j<8; j = j+1)
counter_p[j]<= counter[{sel[N_BITS-1:3], j[2:0]}];
and
for (j=0; j<8; j = j+1)
case (sel[N_BITS-1:3])
3'h0: counter_p[j]<= counter[{3'h0, j[2:0]}];
3'h1: counter_p[j]<= counter[{3'h1, j[2:0]}];
3'h2: counter_p[j]<= counter[{3'h2, j[2:0]}];
3'h3: counter_p[j]<= counter[{3'h3, j[2:0]}];
3'h4: counter_p[j]<= counter[{3'h4, j[2:0]}];
3'h5: counter_p[j]<= counter[{3'h5, j[2:0]}];
3'h6: counter_p[j]<= counter[{3'h6, j[2:0]}];
3'h7: counter_p[j]<= counter[{3'h7, j[2:0]}];
endcase // case (sel[N_BITS-1:3])

is....
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
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