inferring a dual port memory

V

Verictor

Guest
Hi,

I try to infer a dual port RAM after synthesis. DesignWare maybe a
good candidate doing this but I have never used it before. So if
someone who had applied it before can provide a very simple example
that would be very helpful.

My dual port RAM model is described in the following pseudo code
(detail skipped)

always @(posedge clock) begin : read
Temp_reg <= memory[address];
end

always @(negedge clock) begin: write
memory[address] <= Temp_reg;
end

Thanks
 
"Verictor" <stehuang@gmail.com> wrote in message
news:1175718685.646715.316630@w1g2000hsg.googlegroups.com...
Hi,

I try to infer a dual port RAM after synthesis. DesignWare maybe a
good candidate doing this but I have never used it before. So if
someone who had applied it before can provide a very simple example
that would be very helpful.

My dual port RAM model is described in the following pseudo code
(detail skipped)

always @(posedge clock) begin : read
Temp_reg <= memory[address];
end

always @(negedge clock) begin: write
memory[address] <= Temp_reg;
end

Thanks
Click to expand...
As long as the address is a registered value, synthesizers such as
SynplifyPro will infer the dual-port for an FPGA target.

If you're working with an ASIC target, it is very specific to your tool set
and target silicon as far as what infers, what doesn't, and how.
 
On Apr 4, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
"Verictor" <stehu...@gmail.com> wrote in message

news:1175718685.646715.316630@w1g2000hsg.googlegroups.com...



Hi,

I try to infer a dual port RAM after synthesis. DesignWare maybe a
good candidate doing this but I have never used it before. So if
someone who had applied it before can provide a very simple example
that would be very helpful.

My dual port RAM model is described in the following pseudo code
(detail skipped)

always @(posedge clock) begin : read
Temp_reg <= memory[address];
end

always @(negedge clock) begin: write
memory[address] <= Temp_reg;
end

Thanks

As long as the address is a registered value, synthesizers such as
SynplifyPro will infer the dual-port for an FPGA target.

If you're working with an ASIC target, it is very specific to your tool set
and target silicon as far as what infers, what doesn't, and how.
Click to expand...

Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot
 
"Verictor" <stehuang@gmail.com> wrote in message
news:1175786192.075101.272070@o5g2000hsb.googlegroups.com...
<snip>
Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot
Click to expand...
I can't, perhaps someone else can.

The Physical Compiler documentation may include specific documentation on
inferring memories. It's important enough in my FPGA work that the
synthesis tools I work with have several pages dedicated to memory
inference. It may be that you need to instantiate dual ports in this tool.
It may be that you need to have two versions of the address to get the
synthesis to recognize it as two ports rather than a malformed single port
memory; this was a problem for another poster recently. If you can't find
documentation, try the technical support you're already paying dearly for.
 
"John_H" <newsgroup@johnhandwork.com> wrote in message
news:131a7l434cfed92@corp.supernews.com...
"Verictor" <stehuang@gmail.com> wrote in message
news:1175786192.075101.272070@o5g2000hsb.googlegroups.com...
snip
Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot

I can't, perhaps someone else can.

The Physical Compiler documentation may include specific documentation on
inferring memories. It's important enough in my FPGA work that the
synthesis tools I work with have several pages dedicated to memory
inference. It may be that you need to instantiate dual ports in this
tool. It may be that you need to have two versions of the address to get
the synthesis to recognize it as two ports rather than a malformed single
port memory; this was a problem for another poster recently. If you can't
find documentation, try the technical support you're already paying dearly
for.
Click to expand...
In the ASIC world you have to instantiate the specific memory block that you
want to use. The sysnthesizer won't infer a memory ... it will just create
FFs.

Mike
 
On Apr 5, 10:48 am, "Mike Lewis" <some...@micrsoft.com> wrote:
"John_H" <newsgr...@johnhandwork.com> wrote in message

news:131a7l434cfed92@corp.supernews.com...





"Verictor" <stehu...@gmail.com> wrote in message
news:1175786192.075101.272070@o5g2000hsb.googlegroups.com...
snip
Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot

I can't, perhaps someone else can.

The Physical Compiler documentation may include specific documentation on
inferring memories. It's important enough in my FPGA work that the
synthesis tools I work with have several pages dedicated to memory
inference. It may be that you need to instantiate dual ports in this
tool. It may be that you need to have two versions of the address to get
the synthesis to recognize it as two ports rather than a malformed single
port memory; this was a problem for another poster recently. If you can't
find documentation, try the technical support you're already paying dearly
for.

In the ASIC world you have to instantiate the specific memory block that you
want to use. The sysnthesizer won't infer a memory ... it will just create
FFs.

Mike- Hide quoted text -

- Show quoted text -
Click to expand...
Thanks for the comment. Doesn't the DesignWare is coming in to do the
inferring job?
 
On Apr 5, 11:03 pm, "Verictor" <stehu...@gmail.com> wrote:
On Apr 5, 10:48 am, "Mike Lewis" <some...@micrsoft.com> wrote:



"John_H" <newsgr...@johnhandwork.com> wrote in message

news:131a7l434cfed92@corp.supernews.com...

"Verictor" <stehu...@gmail.com> wrote in message
news:1175786192.075101.272070@o5g2000hsb.googlegroups.com...
snip
Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot

I can't, perhaps someone else can.

The Physical Compiler documentation may include specific documentation on
inferring memories. It's important enough in my FPGA work that the
synthesis tools I work with have several pages dedicated to memory
inference. It may be that you need to instantiate dual ports in this
tool. It may be that you need to have two versions of the address to get
the synthesis to recognize it as two ports rather than a malformed single
port memory; this was a problem for another poster recently. If you can't
find documentation, try the technical support you're already paying dearly
for.

In the ASIC world you have to instantiate the specific memory block that you
want to use. The sysnthesizer won't infer a memory ... it will just create
FFs.

Mike- Hide quoted text -

- Show quoted text -

Thanks for the comment. Doesn't the DesignWare is coming in to do the
inferring job?
Click to expand...
For asic design, for memories, generally memory compilers from third
party vendors like artisan/virage etc are used to generate simulation
model/synthesis model/layout hard macro, and instantiated directly
instead of synthesis tool inferring it...
If you allow synthesis tool, it will always implement it using regular
flops with a big area/power penality. By using memories from other
vendors, you have many options like latch based, high density flop
based, true SRAM etc...
I don't think designware compiles memories...
 
On Apr 8, 3:14 am, "rjain" <rja...@gmail.com> wrote:
On Apr 5, 11:03 pm, "Verictor" <stehu...@gmail.com> wrote:





On Apr 5, 10:48 am, "Mike Lewis" <some...@micrsoft.com> wrote:

"John_H" <newsgr...@johnhandwork.com> wrote in message

news:131a7l434cfed92@corp.supernews.com...

"Verictor" <stehu...@gmail.com> wrote in message
news:1175786192.075101.272070@o5g2000hsb.googlegroups.com...
snip
Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot

I can't, perhaps someone else can.

The Physical Compiler documentation may include specific documentation on
inferring memories. It's important enough in my FPGA work that the
synthesis tools I work with have several pages dedicated to memory
inference. It may be that you need to instantiate dual ports in this
tool. It may be that you need to have two versions of the address to get
the synthesis to recognize it as two ports rather than a malformed single
port memory; this was a problem for another poster recently. If you can't
find documentation, try the technical support you're already paying dearly
for.

In the ASIC world you have to instantiate the specific memory block that you
want to use. The sysnthesizer won't infer a memory ... it will just create
FFs.

Mike- Hide quoted text -

- Show quoted text -

Thanks for the comment. Doesn't the DesignWare is coming in to do the
inferring job?

For asic design, for memories, generally memory compilers from third
party vendors like artisan/virage etc are used to generate simulation
model/synthesis model/layout hard macro, and instantiated directly
instead of synthesis tool inferring it...
If you allow synthesis tool, it will always implement it using regular
flops with a big area/power penality. By using memories from other
vendors, you have many options like latch based, high density flop
based, true SRAM etc...
I don't think designware compiles memories...- Hide quoted text -

- Show quoted text -
Click to expand...
This is new to me. Do you have relevant documentation how to
instantiate the models?

Thanks
 
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