inferred ram with initial values

[Alexis GABIN]

Hi everyone,

I use to instantiate all my ram with a own template, but now I would
like the ram to have an initial value (in fact it was first a ROM
declaration but now I want to be able to rewrite the memory) In my rom
description the memory was declared as a constant array of std_logic:

type bloc_memory is array (2**size_adress-1 downto 0) of
std_logic_vector(size_word-1 downto 0) ;

constant bloc_ram : bloc_memory := (others => (others =>'0'));

But to be able to make it rewritable i change the constant to signal , I
think in simulation it will work but do you think it will really
instantiate a ram with an initialized memory?
I don't like to give a value at the declaration of a signal but i see no
other ways to achieve to do my ram. Is there any other way or does these
one is good?


Alexis






Here is the template of my ram :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY RAM_dual_port IS
Generic(
constant size_adress : natural := 12;
constant size_word : natural := 31

);
PORT (
clk_in : in std_logic;
we_in : in std_logic;
adress_in : in std_logic_vector(size_adress-1 downto 0);
data_in : in std_logic_vector(size_word-1 downto 0);
clk_out : in std_logic;
adress_out : in std_logic_vector(size_adress-1 downto 0);
data_out : out std_logic_vector(size_word-1 downto 0)
);
END RAM_dual_port;

architecture behavorial of RAM_dual_port is

type bloc_memory is array (2**size_adress-1 downto 0) of
std_logic_vector(size_word-1 downto 0) ;

signal bloc_ram : bloc_memory := (others => (others =>'0'));

begin

ecriture : process(clk_in)
begin
if rising_edge(clk_in) then
if we_in = '1' then
bloc_ram(to_integer(unsigned(adress_in))) <= data_in;
end if;
end if;
end process ecriture;


lecture : process(clk_out)
begin
if rising_edge(clk_out) then
data_out <= bloc_ram(to_integer(unsigned(adress_out)));
end if;
end process lecture;

end;

 

[Mike Treseler]

Alexis GABIN wrote:

I use to instantiate all my ram with a template,

That's how I do it.

but now I would
like the ram to have an initial value (in fact it was first a ROM
declaration but now I want to be able to rewrite the memory)

The only vendor-independent way to do this
is with separate ROM and RAM inferences.
See my ROM example here:

http://home.comcast.net/~mike_treseler/

But to be able to make it rewritable i change the constant to signal , I
think in simulation it will work but do you think it will really
instantiate a ram with an initialized memory?

No.
RAM is writable by preforming a write cycle.
RAM can only be initialized in a vendor-dependent way.
ROM is not writable.

-- Mike Treseler

 

[Andy]

Initializing inferred ram is a synthesis-tool-specific exercise.
Synplicity allows it, but I don't remember whether it is via
attributes or the signal/variable initializer.

Check your synthesis documentation.

Andy

On Apr 2, 4:57 am, Alexis GABIN <alexis.gabin@_NOSPAM_sptech.com.tw>
wrote:

Hi everyone,

I use to instantiate all my ram with a own template, but now I would
like the ram to have an initial value (in fact it was first a ROM
declaration but now I want to be able to rewrite the memory) In my rom
description the memory was declared as a constant array of std_logic:

type bloc_memory is array (2**size_adress-1 downto 0) of
std_logic_vector(size_word-1 downto 0) ;

constant bloc_ram : bloc_memory := (others => (others =>'0'));

But to be able to make it rewritable i change the constant to signal , I
think in simulation it will work but do you think it will really
instantiate a ram with an initialized memory?
I don't like to give a value at the declaration of a signal but i see no
other ways to achieve to do my ram. Is there any other way or does these
one is good?

Alexis

Here is the template of my ram :

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY RAM_dual_port IS
Generic(
constant size_adress : natural := 12;
constant size_word : natural := 31

);
PORT (
clk_in : in std_logic;
we_in : in std_logic;
adress_in : in std_logic_vector(size_adress-1 downto 0);
data_in : in std_logic_vector(size_word-1 downto 0);
clk_out : in std_logic;
adress_out : in std_logic_vector(size_adress-1 downto 0);
data_out : out std_logic_vector(size_word-1 downto 0)
);
END RAM_dual_port;

architecture behavorial of RAM_dual_port is

type bloc_memory is array (2**size_adress-1 downto 0) of
std_logic_vector(size_word-1 downto 0) ;

signal bloc_ram : bloc_memory := (others => (others =>'0'));

begin

ecriture : process(clk_in)
begin
if rising_edge(clk_in) then
if we_in = '1' then
bloc_ram(to_integer(unsigned(adress_in))) <= data_in;
end if;
end if;
end process ecriture;

lecture : process(clk_out)
begin
if rising_edge(clk_out) then
data_out <= bloc_ram(to_integer(unsigned(adress_out)));
end if;
end process lecture;

end;