Inexplicable compilation error

[better_cs_now@yahoo.com]

Hello all,

I'm using Active HDL 6.3, student edition.

In the code below, I'm getting the following error:

# Error: COMP96_0078: full_adder.vhd : (22, 10): Unknown identifier
"std_logic".

This error occurs in the declaration of entity foo. Note that std_logic
is found just fine prior to this point in the declaration of entity
full_adder. What on earth is going on?

Thanks in advance,
Dave



library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port(
a, b, cin : in std_logic;
s, cout : out std_logic
);
end entity full_adder;

entity foo is
port(
f: in std_logic
);
end entity foo;

 

[Duane Clark]

better_cs_now@yahoo.com wrote:

Hello all,

I'm using Active HDL 6.3, student edition.

In the code below, I'm getting the following error:

# Error: COMP96_0078: full_adder.vhd : (22, 10): Unknown identifier
"std_logic".

This error occurs in the declaration of entity foo. Note that std_logic
is found just fine prior to this point in the declaration of entity
full_adder. What on earth is going on?

It is one of the stranger things in VHDL. You need to redeclare the
libraries before each entity. That's just the way it works

 

[Andy]

The scope of the context clause (library and use statements) is
independent of the file. It is limited to the design unit immediately
following, in this case: full_adder. Note that architectures and
package bodies inherit the scope of their associated entity and package
declaration, regardless of whether those secondary units are located in
the same file as their associated primary units.

This behavior was borrowed from ada.

Andy


better_cs_now@yahoo.com wrote:

Hello all,

I'm using Active HDL 6.3, student edition.

In the code below, I'm getting the following error:

# Error: COMP96_0078: full_adder.vhd : (22, 10): Unknown identifier
"std_logic".

This error occurs in the declaration of entity foo. Note that std_logic
is found just fine prior to this point in the declaration of entity
full_adder. What on earth is going on?

Thanks in advance,
Dave



library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port(
a, b, cin : in std_logic;
s, cout : out std_logic
);
end entity full_adder;

entity foo is
port(
f: in std_logic
);
end entity foo;