Industry publication for Verilog verification tool

Hello,

I'm a University of Michigan student working on a program that parses
Verilog for common design errors, like declaring an output but never
assigning to it, or omitting a port when instantiating a module. The
project is open source, and we definitely will be putting it online,
but we were wondering if there is a Verilog industry publication that
would make sense to submit a writeup of our project to. Any
suggestions?

Thanks,
Zach

 

[vertreko]

On Mar 16, 9:38 am, ste...@gmail.com wrote:

we were wondering if there is a Verilog industry publication that
would make sense to submit a writeup of our project to. Any
suggestions?

You could try http://www.edn.com ,
http://www.eetimes.com ,
or even http://www.deepchip.com