This is rather an open-ended question, unfortunately. I've absolutely no
Hi everyone,Hi Myriam,
I'm not an expert in inductors but I'm trying to give you some clues I
learned over my past experiences.
First of all, you should know what your inductor is going to be used
for. Usually, Small-valued, precise, high-Q inductors are employed in
circuits such as RF transceivers. Larger, lower-Q devices have
functions such as impedance matching and gain control.
The second step is then to define your topology. An inductor can be
drawn in different forms: 1-loop inductor, meander, Spiral (square or
circular), octagonal. You can even have transmission line inductor,
which is the very simple one ;-) . Anyway, your design target is the
main driver.
If we take the Spiral inductor as an example, then a minimum of two
metal layers is required, one to form the spiral and the other to form
the underpass. To minimize parasitic capacitance to the substrate, the
top metal layer is the usual choice for the main spiral. If your
process offers a thick Top metal, this is preferable as well because
it is less resistive. If your process offers both Aluminum and Copper
BE, the copper is more suitable. You can also add a ground-shield
pattern if required. It truly depends on your specifications.
To build the Parametrized cell, you should define the user parameters
the designers have to play with. The common used parameters for
inductors are : The number of turns, coil width (w), spacing
between spirals (s), Total Length/Area ...
If the purpose of your inductor is to achieve a High Q factor, note
that : determining the geometry and area required to deliver an
optimized Q at the design frequency is not a straightforward process.
The most difficult factor in inductor process design is minimization
of the impact of parasitic elements. Real inductors have parasitic
resistance and capacitance. The parasitic resistance dissipates energy
through ohmic loss, while the parasitic capacitance stores unwanted
energy.
At high frequencies, the skin effect causes a nonuniform current
distribution in the metal segments, which introduces (among other
factors) a frequency-dependent contribution to the parasitic
resistance. Furthermore, electromagnetic effects caused by the Faraday
effect
introduce parasitic currents (eddy currents) in the silicon as well,
adding an additional frequency dependency in the resistance.
You can find more information in the following Book : Device Modeling
for Analog and RF CMOS Circuit Design.
From a Skill programming point of view, inductors are not the easiest
pcells to code but are very challenging. The Cadence documentation is
the best resource to help you in figuring out this task. I know
however that Virtuoso Layout offers the possibility to create
Graphical Pcells. I hae used this feature in my young days. I don't
know how much this will be useful for your inductor case but I think
it is worthy to give it a try, to create a starting script at least.
Invoke this tool from : Virtuoso Layout -> Tools -> Pcell. This will
add a menu Pcell to your menu bar.
The idea behind this tool is to create a general outlook fixed layout
and then use some tools to make your fixed layout a Pcell. These are
some notes that helped me in the past times to make Stacked capacitor
Graph Pcells. You might need to adapt it a bit for your inductor
needs :
1 Creation of the general outlook of the pcell
+ Draw a fixed layout view that corresponds to a specific geometry.
For the contacts and the vias, draw only one shape ; the repetition
tool will enable the creation of matrix.
+ The origin of the pcell is located at the coordinates (0 , 0).
+ Add the stretch lines Stretch - Stretch in X/Y
- Select the function
- Draw the stretch line (vertical line for a horizontal stretch)
- Enter the name of the variable and the corresponding length/width in
micron
=> The stretch line appears in yellow
+ By default all the shapes are streched. If some of them are fixed,
you have to use the "qualify" function from the strech menu.
- Select the strech line that is concerned by this operation
( vertical line corresponds to the strech in the X axis).
- Select all the shapes/layers that have to be stretched.
- Press "Return" to finish the operation.
2 Contact/Via array creation
+ This can be done using the "Repetition" tool
- Select the tool and select the via or contact to be duplicated
- Give the pitch (contact width + spacing) between 2 consecutive
shapes.
- Give the number of repetition. It is the result of a calculation
that depends on the pitch and the input parameters of the pcell.
Repeat this operation for each contact/via array
3 Label creation
+ This can be done using the "Parameterized label" function.
=> sprintf("comments %f .... " variable1 variable2)
4 Parameter summary
+ To have the summary of the properties :
PCells -> Parameters -> Summarize
5 Save
To save the pcell :
PCell --> Compile --> To PCell / Skill
Once again, I'm not the expert of this topic and the steps I described
just above are quit old. Cadence people and Pcell documentation are
the best sources for an up to date and optimized way to do this job.
Good Luck !
mariam_telnet wrote:
Hi to all,
I want to realize an inductor with the Skill Langage. Can any one help
me and take me the essential steps to realize this work.
I want the programm in Skill, if it is possible.
Thanks.- Hide quoted text -
- Show quoted text -
, coil width (w), spacing