individual DEFINE file in DC

I put my DEFINE in an individual file. Simulation is OK.
But how to deal with it in DC?

Thanks in advance.

 

[Mike Lewis]

concatenate your "read_verilog" into a single statement.

ie. read_verilog {define.v one.v two.v three.v}

instead of
read_verilog define,v
read_verilog one.v
read_verilog two.v
etc

Mike


<mpub@sohu.com> wrote in message
news:1106796507.300663.263640@c13g2000cwb.googlegroups.com...

I put my DEFINE in an individual file. Simulation is OK.
But how to deal with it in DC?

Thanks in advance.

 

Thanks a lot.

It works well.


Mike Lewis wrote:

concatenate your "read_verilog" into a single statement.

ie. read_verilog {define.v one.v two.v three.v}

instead of
read_verilog define,v
read_verilog one.v
read_verilog two.v
etc

Mike


mpub@sohu.com> wrote in message
news:1106796507.300663.263640@c13g2000cwb.googlegroups.com...
I put my DEFINE in an individual file. Simulation is OK.
But how to deal with it in DC?

Thanks in advance.