Indirect assignment.

[titi]

In the following example, what would do the xxx assignment?
What would be the effect of removing the xxx and doing direct assignment?


process(Reset,Pulse,e1,Val)
begin
if Reset ='1' then
result <= "0000";
elsif Pulse ='1' and Val = 25 then
xxx <= e1(3 downto 0);
result <= xxx;
end if;
end process;

 

[KJ]

On Mar 12, 10:14 am, titi <t...@nospam.fr> wrote:

In the following example, what would do the xxx assignment?
The line that has "xxx <= " on it, but xxx wouldn't get updated until

the end of the process has been reached.

What would be the effect of removing the xxx and doing direct assignment?
It would behave differently.

Use a simulation tool and you'll see and decide for yourself what is
the correct behaviour for your particular application.

KJ

 

[Pieter Hulshoff]

titi wrote:

In the following example, what would do the xxx assignment?
What would be the effect of removing the xxx and doing direct assignment?


process(Reset,Pulse,e1,Val)
begin
if Reset ='1' then
result <= "0000";
elsif Pulse ='1' and Val = 25 then
xxx <= e1(3 downto 0);
result <= xxx;
end if;
end process;

You will probably get a warning on this piece of code telling you that
xxx should be in the sensitivity list. Currently this code will probably
not function the way you had intended it to. A direct assignment will
most likely give you the intended behavior.

The current code will only execute under a CHANGE of the signals in the
sensitivity list. This implies that when pulse becomes '1', xxx will be
updated with e1(3 downto 0), but this value won't be seen on the output
result unless one of the signals in the sensitivity list changes value
while the conditions hold true (reset = '0' and pulse = '1' and val =
25). Putting xxx in the sensitivitiy list will make the process execute
again one delta time later, and xxx will be copied to the result output.

Regards,

Pieter Hulshoff

 

[Ralf Hildebrandt]

titi schrieb:

In the following example, what would do the xxx assignment?

"Do" in terms of behavior? -> Use a simulator.
"Do" in terms of synthesis? -> Use a synthesis tool and have a look.

What would be the effect of removing the xxx and doing direct assignment?

process(Reset,Pulse,e1,Val)
begin
if Reset ='1' then
result <= "0000";
elsif Pulse ='1' and Val = 25 then
xxx <= e1(3 downto 0);
result <= xxx;
end if;
end process;

xxx will become a latch (this means a memory element) if you read xxx
somewhere else. If you don't read it somewhere else then the synthesis
tool will remove xxx because it is useless.

As Pieter states the sensitivity list is incomplete. If you add xxx to
it, you will observe during simulation that e1 will be feed through to
result via xxx. Note that synthesis and simulation will result in
different behavior with an incomplete sensitivity list!


Let me add: result is a latch and you will run into the muxed-latch
problem. This means, a mux choses the value to load into a latch, but
both the mux-selector as well as the latch-enable are driven by the same
signals. If the latch-enable becomes inactive, the mux may change its
output too and this may be faster than closing the latch. To get rid of
this, seperate the mux-selector and the latch-enable! How to do it is
your task. I can only give you the hint, that the mux chooses between
"0000" and e1(3 downto 0) and the latch is loaded with the output of the
mux if reset='1' or if (pulse='1' and val=25). You have to find some
_different_ signal that serves as the mux-selector! A signal, that is
stable if reset becomes inactive AND pulse becomes inactive AND val gets
a different value.

Latches are wonderful for low-power small-area designs, but as you see
they are difficult to handle.

Ralf

 

[Mark McDougall]

Ralf Hildebrandt wrote:

Note that synthesis and simulation will
result in different behavior with an incomplete sensitivity list!

Simulation - yes, but synthesis?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Ralf Hildebrandt]

Mark McDougall schrieb:

Ralf Hildebrandt wrote:

Note that synthesis and simulation will
result in different behavior with an incomplete sensitivity list!

Simulation - yes, but synthesis?

(Maybe I trapped into a pitfall of the language. English is not my
native language.)

Synthesis ignores the sensitivity list and acts as the sensitivity list
would be complete. Therefore behavioral simulation and post-synthesis
simulation will result different behavior.

Ralf

 

[Mark McDougall]

Ralf Hildebrandt wrote:

(Maybe I trapped into a pitfall of the language. English is not my
native language.)

Synthesis ignores the sensitivity list and acts as the sensitivity list
would be complete. Therefore behavioral simulation and post-synthesis
simulation will result different behavior.

Yes, I only realised myself after reading your reply that your statement
was ambiguous, and could be taken either way.

Isn't English wonderful!?!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266