Indexing bit-vectors using variables

[Brendan]

Hi.

I'm trying to access a bit-vector slice using variables, like:

data_in [ (index+8): index]

But my compiler tells me this must be done using constants.

Anyonr know a way around this?

Thanks in advance,

Brendan

 

[David Jones]

In article <fd435d51.0311240301.50c0ba46@posting.google.com>,
Brendan <brendan@comodogroup.com> wrote:

Hi.

I'm trying to access a bit-vector slice using variables, like:

data_in [ (index+8): index]

But my compiler tells me this must be done using constants.

In Verilog, the expressions in part-selects must be constants. Otherwise,
the compiler cannot determine the final size of the expression.

Workarounds:

1. If you have access to Verilog-2001, then use the new variable
part-select operator:

data_in[index +: 9]

2. If not, use shifting:

assign temp = data_in >> index;

 

[Anthony J Bybell]

brendan@comodogroup.com (Brendan) wrote in message news:<fd435d51.0311240301.50c0ba46@posting.google.com>...

Hi.

I'm trying to access a bit-vector slice using variables, like:

data_in [ (index+8): index]

But my compiler tells me this must be done using constants.

Anyonr know a way around this?

Thanks in advance,

Brendan

As a quick and dirty general purpose solution, a barrel shifter comes
to mind: assuming little-endian bit ordering, you'd shift right the
count of index and pick off the lowest nine bits (+8 : +0).

Much does depend on how you access data_in. Do you always access the
bits at their natural alignment (i.e., 0, 9, 18, ...)? If so and
data_in isn't very wide, a decoder structure with AOs might fit the
bill.

Is this for simulation on synthesis? That's a key point you neglect
to mention.

There's also the possibility of instantiating a memory instead if
that's possible (i.e., you're not attempting to grab a subset of bits
generated from random logic).

-t

 

[Swapnajit Mittra]

brendan@comodogroup.com (Brendan) wrote in message news:<fd435d51.0311240301.50c0ba46@posting.google.com>...

Hi.

I'm trying to access a bit-vector slice using variables, like:

data_in [ (index+8): index]

But my compiler tells me this must be done using constants.

Anyonr know a way around this?

Thanks in advance,

Brendan

reg [7:0] temp;
....
temp = data_in >> index;

--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/

 

[Brendan]

Thanks everyone!

 

[Bob Brandt]

I am facing the same problem that Brendan posted. That looks like a good
solution. I haven't tried it yet because I have a few more questions
about it.

1) Can assignments be made into the array? I would guess a temp copy of
the entire array can be made, then modified with ANDing and ORing in the
changes with shifting.

2) I also need to variably index instances as well as memories. I don't
imagine those can be shifted. For example, the design is an array of
instances that each have a memory and I want to initialize all of them:
top.inst.mem[j] = 16'h0;
with i and j set by nested for loops.

3) In a similar situation to 2) is there a way of looping over instances
that aren't arrayed but rather are instantiated longhand? For example
top.inst0.mem[j] = 16'h0;
top.inst1.mem[j] = 16'h0;
....etc.
Perhaps some sort of sprintf statement whose output can be used as the
hierarchical path on the left-hand side of an assignment?

Thanks in advance for any help,
Bob


Swapnajit Mittra wrote:

brendan@comodogroup.com (Brendan) wrote in message news:<fd435d51.0311240301.50c0ba46@posting.google.com>...


Hi.

I'm trying to access a bit-vector slice using variables, like:

data_in [ (index+8): index]

But my compiler tells me this must be done using constants.

Anyonr know a way around this?

Thanks in advance,

Brendan



reg [7:0] temp;
...
temp = data_in >> index;

--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/