Indexing a vector using variables?

[Brendan Lynskey]

Hi.

I'm trying to access a vector slice using variables for indices, but my
(Modelsim) compiler doesn't allow it. This is the kind of thing I want to
do:

for (index = 16'h0; index < 16'h43; index = index + 16'h1)
begin
op_var = data_vect[ (index + 16'h8) : index];
...
end

The compiler tells me:

ERROR: Range must be bounded by constant expressions



Anyone know a way around this?

--

Best regards

Brendan Lynskey
ASIC Engineer - Comodo Research Lab
Invent ˛ Secure
www.comodogroup.com, www.trustix.com, www.enterprisessl.com, www.seeos.com

 

[Jonathan Bromley]

"Brendan Lynskey" <brendan@comodogroup.com> wrote in
message news:bpg62h$v3v$1@kylie.comodogroup.com...

I'm trying to access a vector slice using variables for indices, but my
(Modelsim) compiler doesn't allow it. This is the kind of thing I want to
do:

for (index = 16'h0; index < 16'h43; index = index + 16'h1)
begin
op_var = data_vect[ (index + 16'h8) : index];
...
end

The compiler tells me:

ERROR: Range must be bounded by constant expressions

hi Brendan,

it's not ModelSim, it's Verilog that disallows variable
bounds to a part-select. Of course, your part-select is
of fixed width, which makes perfect sense in both
hardware and simulation; but the rules were written like
that to protect against getting dynamically varying
operand widths.

That's why Verilog-2001 added the "variable base, fixed
width" formulation for a part-select. In your
example:

op_var = data_vect[index +: 8];

ModelSim has been supporting this since at least
version 5.7c (and possibly earlier). You don't even
need to activate any command-line switch.

If you have tools that don't support this, you could always
rewrite the part-select as a for loop:

for (index = .....) begin: InnerLoop
integer bit_num;
for (bit_num = 8; bit_num >= 0; bit_num = bit_num-1)
op_var[bit_num] = data_vect[bit_num+index];
...
end // InnerLoop

If you do this, watch very carefully for synth tools
making a mess of the indexing, like (for example) trying
to build an adder to create [bit_num+index]. Sometimes
there are other ways to code up this kind of thing,
that don't require the implied barrel shifter.

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in
message news:bpg8r3$6ll$1$830fa7a5@news.demon.co.uk...

for (index = 16'h0; index < 16'h43; index = index + 16'h1)
begin
op_var = data_vect[ (index + 16'h8) : index];

That's why Verilog-2001 added the "variable base, fixed
width" formulation for a part-select. In your
example:

op_var = data_vect[index +: 8];

whoops, that'll be [index +: 9] given your [8:0] original.
The second operand in the [base : length] scheme is the
total number of bits you want.

Off-by-one, the curse of digital design...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Cliff Cummings]

Jonathan has given the Verilog-2001 technique to solve this problem.
Most variable indexes can be expressed using Verilog-1995 shift
operations and they synthesize rather nicely.

// Takes advantage of Verilog automatic truncation
// NOTE: or index+9, depending on actual requirement
for (index=0; index<16'h43; index=index+8) begin
opvar = data_vect>> index;
...
end

Regards - Cliff Cummings

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
Verilog On-Site Training Sale - 4-day Courses for $1,200/Student
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


"Brendan Lynskey" <brendan@comodogroup.com> wrote in message news:<bpg62h$v3v$1@kylie.comodogroup.com>...

Hi.

I'm trying to access a vector slice using variables for indices, but my
(Modelsim) compiler doesn't allow it. This is the kind of thing I want to
do:

for (index = 16'h0; index < 16'h43; index = index + 16'h1)
begin
op_var = data_vect[ (index + 16'h8) : index];
...
end

The compiler tells me:

ERROR: Range must be bounded by constant expressions



Anyone know a way around this?