S
Salman
Guest
I have a vhdl value that I must test whether it increments by one. The
input signal is a 32-bits count value (std logic vector). My module
would receive this value as an input to check whether it increments and
that would affect the state machine.
How would I code something like this as efficiently as possible?
Salman
input signal is a 32-bits count value (std logic vector). My module
would receive this value as an input to check whether it increments and
that would affect the state machine.
How would I code something like this as efficiently as possible?
Salman