Increasing the Global Clock value inside the design ?

[anil]

Hello,

I have a question relating to Clocks. If i have a clock with
frequency Fs . I want to generate another clock with frequency N*Fs.
How is this done in VHDL.

or is it that i must have another clock input with this frequency.

also suggest me which method is the better of the above two .

Thanking you in advance.

Regards,
J.Anil Kumar.

 

[Eric]

With any descriptive langauge (VHDL, Verilog) you can't generate a
clock faster than the one used in the sensitivity list.

You could use both rising and falling edge to create a 2x clock, but
I've read that using both edges is not good practice for synthesis.

You could instantiate a Xilinx DCM and use that to multiply the clock,
or an Altera PLL. These are hardware blocks built into the FPGA's that
allow for clock multiplication/ division.

Eric