J
Jan Decaluwe
Guest
The other day I was glancing over the ModelSim Users Manual, v6.5e
and I saw something strange.
They explain nondeterminism caused by blocking assignments with the
following example (p. 250):
1. always@(q) p = q;
2. always @(q) p2 = not q;
3. always @(p or p2) clk = p and p2;
with p=0, p2=1, and q going from 0->1.
Depending on the execution order, always block 3 may be triggered with
inconsistent values of p and p2 (both 1), or not. So you may have
glitch on clk, or not. Hence this model is nondeterministic, and they
call this a race condition.
Then, on p. 252, they state (between brackets):
"In the preceding example, changing all statements to non-blocking
assignments would not remove the race condition".
I'm not a Verilog event scheduling specialist , but I think it
would. With non-blocking assignments, p and p2 would always trigger
block 3 with the same values, irrespective of the execution order of
the always blocks. Hence the model would be deterministic.
Or am I missing something about Verilog again ;-) ?
Jan
and I saw something strange.
They explain nondeterminism caused by blocking assignments with the
following example (p. 250):
1. always@(q) p = q;
2. always @(q) p2 = not q;
3. always @(p or p2) clk = p and p2;
with p=0, p2=1, and q going from 0->1.
Depending on the execution order, always block 3 may be triggered with
inconsistent values of p and p2 (both 1), or not. So you may have
glitch on clk, or not. Hence this model is nondeterministic, and they
call this a race condition.
Then, on p. 252, they state (between brackets):
"In the preceding example, changing all statements to non-blocking
assignments would not remove the race condition".
I'm not a Verilog event scheduling specialist , but I think it
would. With non-blocking assignments, p and p2 would always trigger
block 3 with the same values, irrespective of the execution order of
the always blocks. Hence the model would be deterministic.
Or am I missing something about Verilog again ;-) ?
Jan