Guest
Hi all,
In this Verilog code, clk1 is correctly lifted high at t = 5, but clk2
is not lifted high at t = 10. Instead, it goes high at t = 15, even
though *all* assignments are non blocking. This program, though, works
correctly using the fork-join construct. Any ideas why is it so ??? I
am using NCVerilog compiler and Simvision viewer.
module surprise (clk1, clk2);
output clk1, clk2;
reg clk1, clk2;
initial
begin
clk1 <= 1'b0;
clk2 <= 1'b0;
#5 clk1 <= 1'b1;
#10 clk2 <= 1'b1;
#15 $finish;
end
initial
begin
$shm_open ("surprise.shm");
$shm_probe ("as");
end
endmodule
Best regards,
Amit.
In this Verilog code, clk1 is correctly lifted high at t = 5, but clk2
is not lifted high at t = 10. Instead, it goes high at t = 15, even
though *all* assignments are non blocking. This program, though, works
correctly using the fork-join construct. Any ideas why is it so ??? I
am using NCVerilog compiler and Simvision viewer.
module surprise (clk1, clk2);
output clk1, clk2;
reg clk1, clk2;
initial
begin
clk1 <= 1'b0;
clk2 <= 1'b0;
#5 clk1 <= 1'b1;
#10 clk2 <= 1'b1;
#15 $finish;
end
initial
begin
$shm_open ("surprise.shm");
$shm_probe ("as");
end
endmodule
Best regards,
Amit.