Inconsistencies in hpiceS netlist extraction in ADE

Hi,

I synthesized a finite state machine and tried running a Spectre
circuit-level simulation on the synthesized netlist. Although the
simulation took a long time, it eventually gave me the expected
results. To speed up the simulations (for other larger sims), I decided
to use HSim. So, I extracted an hspiceS netlist from Analog
environment, and used it to run an indentical simulation in Hsim.

The results of this simulation was different from what I was expecting.
To make sure there isn't something wrong with my HSim setup, I ran an
Hspice and then a "spectre +csfe" simulation on the extracted spice
netlist. In all cases, I got the same (but incorrect) outputs. The
problem seems to be in the extraction of the hspiceS netlist in the
Analog environment.

Any ideas as to what may be going wrong ? Just to be sure, I ran some
Hsim simulations on some analog designs (like a PLL) using the same
flow, and Spectre and HSim seem to agree perfectly. So my hunch is it
is something to do with the design being a state machine.

Any helpful tips will be greatly appreciated.

Thanks,
Ankur

 

[Andrew Beckett]

On 16 Jan 2007 12:45:11 -0800, ankur101@gmail.com wrote:

Hi,

I synthesized a finite state machine and tried running a Spectre
circuit-level simulation on the synthesized netlist. Although the
simulation took a long time, it eventually gave me the expected
results. To speed up the simulations (for other larger sims), I decided
to use HSim. So, I extracted an hspiceS netlist from Analog
environment, and used it to run an indentical simulation in Hsim.

The results of this simulation was different from what I was expecting.
To make sure there isn't something wrong with my HSim setup, I ran an
Hspice and then a "spectre +csfe" simulation on the extracted spice
netlist. In all cases, I got the same (but incorrect) outputs. The
problem seems to be in the extraction of the hspiceS netlist in the
Analog environment.

Any ideas as to what may be going wrong ? Just to be sure, I ran some
Hsim simulations on some analog designs (like a PLL) using the same
flow, and Spectre and HSim seem to agree perfectly. So my hunch is it
is something to do with the design being a state machine.

Any helpful tips will be greatly appreciated.

Thanks,
Ankur

Perhaps there is some subtle problem with the hspiceS simInfo in the CDF for one
(or more) of the devices you have in the design that is showing the problems.
You probably need to carefully inspect the resulting netlist and compare it
against the spectre netlist to see if you can spot the error.

It's unlikely to be something to do with the design being a finite state machine
- I can't see how the netlister would know to do something wrong based on the
type of design! More likely it is something to do with a component not being
netlisted properly, and the simulation of that design being sensitive to that
error?

Does your design kit support the newer hspiceD interface? (hspiceS is obsolete).
If so, does that work instead?

Regards,

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.