Including netlists for AMS

First off, please excuse my ignorance in this matter. Up until now, I
would simply create a schematic, open up ADE setup for Spectre, ask it
to compile me a netlist, and I would then setup and run my simulation
from the command line. I never before created schematic testbenches;
all of my testbenches were textual in nature. All of my simulations
were straight Spectre.

Well, now I've been placed in the situation where I have tens of
thousands of transistors, and straight Spectre sims just don't cut it
anymore. Thus, I'm moving over to doing simulations in AMS, and am
becoming familiar with running everything from the GUI. I've already
proven AMS, first with just a two component circuit, and then with
another circuit I'm working on that doesn't have a lot of inputs to it.
Thus, creating a testbench was fairly simple. Now, I want to move the
complexity up even another level.

I have a circuit with a massive number of inputs. For the Spectre
sims, I would place an include statement in my deck that pointed to a
file containing the definition for a couple hundred PWL voltage
sources. This way, I didn't have to deal with the GUI for defining
these pseudo-random bitstreams. For AMS, I thought that I could just
make a symbol with the correct number of ports on it, place it in a
testbench schematic, and then for the 'View to Use', point AMS at my
source file that contains the information for the PWL voltage sources.
However, the elaborator chokes on this.

I read some of the other posts regarding attaching netlists to symbols,
and they don't seem to quite fit what I need, but like I said, I'm
ignorant as to how to properly set this up.

Jake

 

[Svenn Are Bjerkem]

On Oct 17, 2:44 am, wegman.j...@gmail.com wrote:

First off, please excuse my ignorance in this matter. Up until now, I
would simply create a schematic, open up ADE setup for Spectre, ask it
to compile me a netlist, and I would then setup and run my simulation
from the command line. I never before created schematic testbenches;
all of my testbenches were textual in nature. All of my simulations
were straight Spectre.

I hope you allow a little return question here: You say you use ADE,
that means that you fire up that window with the yellow and the green
traffic light, and that all you use this interface for is to generate a
netlist, presumably with the recreate netlist. Then ADE fire up another
window showing you an all-inclusive spectre netlist. This one you
either cut-and-paste or save-as somewhere else where you then go on
with the simulations? This is just for me to get a feeling how you work
with the tools.

[snip]

I have a circuit with a massive number of inputs. For the Spectre
sims, I would place an include statement in my deck that pointed to a
file containing the definition for a couple hundred PWL voltage
sources. This way, I didn't have to deal with the GUI for defining
these pseudo-random bitstreams. For AMS, I thought that I could just
make a symbol with the correct number of ports on it, place it in a
testbench schematic, and then for the 'View to Use', point AMS at my
source file that contains the information for the PWL voltage sources.
However, the elaborator chokes on this.

With AMS you can describe your testbench in verilog, why would you work
with pwl?
If you take the hassle to track down the bitgen.pl application, it will
take away some of the work of generating patterns.

I read some of the other posts regarding attaching netlists to symbols,
and they don't seem to quite fit what I need, but like I said, I'm
ignorant as to how to properly set this up.

If all you want to do is to strap a symbol around a spectre netlist
filled up with pwl sources, then those descriptions should fit your
needs.
1. Make the symbol
2. Make the CDF with name and termOrder
3. Copy the symbol view to a spectre view.
4. Include that spectre netlist in the Model Include Dialog.
5. Fire off netlisting.
6. Simulate.

I think there has been mentioned a couple of times that one doesn't
need the spectre cell view, but in all my experience I have needed it.

But again, if you go the AMS way it is way better to code verilog in my
opinion.
--
Svenn

 

I hope you allow a little return question here: You say you use ADE,
that means that you fire up that window with the yellow and the green
traffic light, and that all you use this interface for is to generate a
netlist, presumably with the recreate netlist. Then ADE fire up another
window showing you an all-inclusive spectre netlist.

I've actually used both the AMS plug-in for the Hierarchy Editor and
the ADE. For all Spectre stuff, I run off of the command line. I know
this can be done for AMS, but everyone I've talked to is more
comfortable with the GUIs for this one, so that's the route I'm going.

With AMS you can describe your testbench in verilog, why would you work
with pwl?
If you take the hassle to track down the bitgen.pl application, it will
take away some of the work of generating patterns.

I already have the pwl sources made from my Spectre sims. Since I went
through the trouble to write a script to create the input for Spectre,
it doesn't seem worth the trouble for me to back and code that in
Verilog, especially since I'm just now picking up Verilog. I'm 100%
analog by trade .

If all you want to do is to strap a symbol around a spectre netlist
filled up with pwl sources, then those descriptions should fit your
needs.
1. Make the symbol
2. Make the CDF with name and termOrder
3. Copy the symbol view to a spectre view.
4. Include that spectre netlist in the Model Include Dialog.
5. Fire off netlisting.
6. Simulate.

Which Model Include Dialog? Is then when I make the CDF?

Thanks,
Jake

 

[Svenn Are Bjerkem]

On Oct 18, 11:26 pm, wegman.j...@gmail.com wrote:

Which Model Include Dialog? Is then when I make the CDF?

You will find this in ADE->Setup->Model Libraries...
--
Svenn

 

I follow all of these step and the netlister crashes when it sees the
symbol. What exactly do you mean when you say 'copy symbol view to
spectre view'? Is this through the library manager? Us there any
information outside of the port order that CDF needs to make this all
work?

Thanks,
Jake

 

[Svenn Are Bjerkem]

wegman.jake@gmail.com wrote:

I follow all of these step and the netlister crashes when it sees the
symbol. What exactly do you mean when you say 'copy symbol view to
spectre view'? Is this through the library manager? Us there any
information outside of the port order that CDF needs to make this all
work?

Yes, I mean the library manager.

Don't forget to set the base view combo at the top of the CDF ,
otherwise all changes are gone by next start of icfb.

After you have finished creating your symbol with whatever text and
graphic and pins (use the "add pin" function, don't place ipin and opin
by hand.) in your "symbol" cellview, _and_ (in my experience) added the
subcircuit name and the termOrder to the CDF that match your simulator
(you will have to drop down "spectre"on that little button above all
those empty entries.)

Right-click on the "symbol" cellview and copy to "spectre" cellview.

If the netlister give you any error message when it crashes, I want to
know what it says.

I recommend to have the comphelp.pdf open as many of these things are
described in there.

--
Svenn

 

Finally got it. The problem seems to be with the way the CDF handles
buses (or doesn't handle them?). I have 256 outputs with the label
Out<0:255>. So, I placed this in the termOrder field. The netlister
chokes on this, but doesn't tell me why it chokes. So, using SKILL, I
tell it to dump the information (cdfDump) and then edit it accordingly
with a script that gets rid of the bus notation and lists everything
individually. I then reload the file, and everything works.

Thanks for your help!
Jake