K
kb33
Guest
Hi,
I have the following sequential and combinational logic:
reg [31:0] job_time_array[0:7]
job_time_array_comb[0:7];
reg v_bit_array[0:7],
v_bit_array_comb[0:7];
//Sequential logic....
always @(posedge sys_clk)
begin
for (i=0; i < 8; i=i+1)
begin
job_time_array <= job_time_array_comb;
v_bit_array <= v_bit_array_comb;
end
//Combinational logic...
always @(reset_n)
begin
if (~reset_n)
for (k=0; k < 8; k=k+1)
job_time_array_comb[k] <= 0;
else
for(k=0; k < 8; k=k+1)
if ((v_bit_array[k] == 1) && (job_time_array[k] > 0))
job_time_array_comb[k] <= job_time_array[k] - 1;
else
job_time_array_comb[k] <= job_time_array[k];
end
My problem is the following: I want the second FOR loop in the
combinational logic to be executed at each clock cycle, but unless
there is something changing in the sensitivity list, this will not
happen. Is there any way to include the whole of job_time_array in the
sensitivity list so that the FOR loop can be executed?
Thanks
Kanchan
I have the following sequential and combinational logic:
reg [31:0] job_time_array[0:7]
job_time_array_comb[0:7];
reg v_bit_array[0:7],
v_bit_array_comb[0:7];
//Sequential logic....
always @(posedge sys_clk)
begin
for (i=0; i < 8; i=i+1)
begin
job_time_array <= job_time_array_comb;
v_bit_array <= v_bit_array_comb;
end
//Combinational logic...
always @(reset_n)
begin
if (~reset_n)
for (k=0; k < 8; k=k+1)
job_time_array_comb[k] <= 0;
else
for(k=0; k < 8; k=k+1)
if ((v_bit_array[k] == 1) && (job_time_array[k] > 0))
job_time_array_comb[k] <= job_time_array[k] - 1;
else
job_time_array_comb[k] <= job_time_array[k];
end
My problem is the following: I want the second FOR loop in the
combinational logic to be executed at each clock cycle, but unless
there is something changing in the sensitivity list, this will not
happen. Is there any way to include the whole of job_time_array in the
sensitivity list so that the FOR loop can be executed?
Thanks
Kanchan