`INCLUDE filename.v

R

rsk

Guest
Dear Friends,

I need to write a generic code for my logic.For this purpose i have to
write a file some where
with the input values and i need to include it to my mail module.If i
change these input values from the earlier case my code should work
with these new values.

I came to know that we can use this
`include filename.v ,But where should i write it and how should i
write and how will it works?

plzz tell me ..

I will be waiting for your Reply...

Thank you,
Rsk...
 
'include file is a normal verilog file with verilog semantics.

suppose:
a.v

-----------------------
module a (x,y,z);
input x;
input y;


-------------------
b.v
---------------------
`include "a.v"
output z;
assign z = x &y;
endmodule
---------------------

if u analyze b.v, then there is no sematic error.
`include file, just includes all the contents of the file a.v in b.v

Hope this example helps.

-Ankur
 
Thank you ankur but in my case i need to use seven different numbers
to seven variables.

like p->10
q->11
r->70
s->14
x->5
y->9
z->51

and i can change the above values anytime

like p->1
q->2
r->41
s->47
x->50
y->19
z->15

but my code should work acordingly.


i think i need to use some "parameter" concept here.But i dont know how
do i have to do it?

will u help me plz

i will be waiting for your reply

thank you,
krs...
 
like p->10
q->11
r->70
s->14
x->5
y->9
z->51

and i can change the above values anytime

like p->1
q->2
r->41
s->47
x->50
y->19
z->15

but my code should work acordingly.
//------------submodule----------------------
module ex1(out2);
parameter p = 10;
parameter q = 11;
assign out2 = p & q;
endmodule

module ex2(out3);
parameter r = 41;
parameter s = 47;
assign out3 = r & s;
endmodule

module ex3(out4);
parameter x = 50;
parameter y = 19;
parameter z = 15;
assign out4 = x & y & z;
endmodule
//-----------main module-----------------------
module main(out5);
parameter p = 1; // don't have to be the same name as submodule's
parameter q = 2;
parameter r = 41;
parameter s = 47;
parameter x = 50;
parameter y = 19;
parameter z = 15;
ex1 #(p, q) // must be the same as their original sequence
example1(out2);
ex2 #(r, s)
example2(out3);
ex3 #(x, y, z)
example3(out4);
assign out5 = out2 | out3 | out4;
// these '|' and '&' are example, you can do any computation you want.

endmodule
//----------------------------------

i think i need to use some "parameter" concept here.But i dont know how
do i have to do it?

will u help me plz

i will be waiting for your reply

thank you,
krs...
Best Regards
 

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