IN the PSL...

[yeah]

here plz give up the idea about use of modeling layer in PSL and its
structure

 

[HT-Lab]

"yeah" <thiyagu.in@gmail.com> wrote in message
news:1175584794.659985.149120@n59g2000hsh.googlegroups.com...

here plz give up the idea about use of modeling layer in PSL and its
structure

AFAIK the modelling layer just specifies that you can use synthesisable VHDL
constructs inside a PSL unit. This was added to allow users to model
hardware that is not part of the design but is required for verification.

example:

vunit my_prop(arch(entity)) {
property....
process -- sequential
begin
....
end process;
generate -- concurrent
...
end generate
}

Hans
www.ht-lab.com

 

[yeah]

hi
thanx..
now its clear...
HT-Lab wrote:

"yeah" <thiyagu.in@gmail.com> wrote in message
news:1175584794.659985.149120@n59g2000hsh.googlegroups.com...
here plz give up the idea about use of modeling layer in PSL and its
structure


AFAIK the modelling layer just specifies that you can use synthesisable VHDL
constructs inside a PSL unit. This was added to allow users to model
hardware that is not part of the design but is required for verification.

example:

vunit my_prop(arch(entity)) {
property....
process -- sequential
begin
....
end process;
generate -- concurrent
...
end generate
}

Hans
www.ht-lab.com