In My verilog Carry Look Ahead Adder(8 bit) code design, fro

I have written verilog code and testbanch for carry look ahead adder. Then compiled in VCS and wrote synthesis script and then in design vision I saw RTL diagram of my circuit. In the input flip-flop's one 8 bit register's one bit is not connected as desired. But other connections defined exactly same are connected perfectly.

always @(posedge clk or negedge rst) begin
if (~rst) begin
am<=8'd0;
bn<=8'd0;
sumv<=8'd0;
cino<=1'b0;
coutv<=1'b0;
end else begin
am<=a;
bn<=b;
cino<=cin;
sumv<=sum;
coutv<=cout;
end
end

 

[GaborSzakacs]

vickydhudashia92@gmail.com wrote:

I have written verilog code and testbanch for carry look ahead adder. Then compiled in VCS and wrote synthesis script and then in design vision I saw RTL diagram of my circuit. In the input flip-flop's one 8 bit register's one bit is not connected as desired. But other connections defined exactly same are connected perfectly.

always @(posedge clk or negedge rst) begin
if (~rst) begin
am<=8'd0;
bn<=8'd0;
sumv<=8'd0;
cino<=1'b0;
coutv<=1'b0;
end else begin
am<=a;
bn<=b;
cino<=cin;
sumv<=sum;
coutv<=cout;
end
end

How are your variables (reg and wire) defined?

Where do "sum" and "cout" come from?

Which bit isn't hooked up as expected?

--
Gabor