In a function, how to I do bit-extension on temp variables:

[Mr. Ken]

Here is my function, which does some custom-made multipliers/division.
NCVerilog simulations for RTL so far shows no problem but design compiler
complains of
this warning.

"Warning: myfile.v:276: Variable 'result' may be read before being
assigned; the synthesized result may not match simulations. (ELAB-391)"

How do I fix this problem?



function [17:0] mult_ck34; // Multiplication for ck3, cl4
input [14:0] sum_row;
input [2:0] multpl_sel;
reg [22:0] result;
begin
case (multpl_sel)
3'b001,
3'b110: begin // 32 + 8 + 2 + 1 // X43>>3
result[20:0] = {{ {sum_row[14]}}, {sum_row}, {5'b0}} + // 32
{{3{sum_row[14]}}, {sum_row}, {3'b0}} + // 8
{{5{sum_row[14]}}, {sum_row}, {1'b0}} + // 2
{{6{sum_row[14]}}, {sum_row}}; // 1
result[22:21] = {2{result[20]}};
end
...
...
endcase
end

mult_ck34 = result[21:4];

endfunction

 

[Rob Dekker]

"Mr. Ken" <Mr. Ken@asdf> wrote in message news:44cd6dba$1@news.starhub.net.sg...

Here is my function, which does some custom-made multipliers/division.
NCVerilog simulations for RTL so far shows no problem but design compiler
complains of
this warning.

"Warning: myfile.v:276: Variable 'result' may be read before being
assigned; the synthesized result may not match simulations. (ELAB-391)"

How do I fix this problem?



function [17:0] mult_ck34; // Multiplication for ck3, cl4
input [14:0] sum_row;
input [2:0] multpl_sel;
reg [22:0] result;
begin
case (multpl_sel)
3'b001,
3'b110: begin // 32 + 8 + 2 + 1 // X43>>3
result[20:0] = {{ {sum_row[14]}}, {sum_row}, {5'b0}} + // 32
{{3{sum_row[14]}}, {sum_row}, {3'b0}} + // 8
{{5{sum_row[14]}}, {sum_row}, {1'b0}} + // 2
{{6{sum_row[14]}}, {sum_row}}; // 1
result[22:21] = {2{result[20]}};
end
...
...
endcase
end

mult_ck34 = result[21:4];

endfunction

Hi Mr. Ken,

You cut out most case items, and there lies the issue:
If in one of the case items you do NOT assign something to 'result' (at least the bits 21:4 which are returned out of the function)
then they can be unassigned for a call to the function.

If that happens (local variable not assigned in a function call), a simulator will simply hold it's old value (from the previous
call).
That is inherited from Verilog's primitive early days : There are no dynamic variables.
All variables, even local ones in a function or task, are 'static' : they come alive at simulation start time, and they die only at
simulation end.

Synthesis tools have a hard time putting this behavior into hardware, since it requires remembering the value between two
function calls. Some synthesis tools correctly create latches or flip-flops to mimic that behavior (and issue correct
multiple assignment errors if there are multiple calls to this function from two concurrent always statements) but others simply
give a
warning and assign an 'x' to the unassigned bits (or something else which does not require remembering last calls' value).

DC apparently is in the second category.
Since there is a difference between synthesis tools in which unassigned variables, it is fair to say that you should probably
re-code this function so that every bit of 'result' is always assigned to something. Even a simple

result = 0

at the start of the function would do the job (of making sure that the function result does not rely on a previous call).

Rob