P
PM
Guest
Hi there,
Is there any way I can implement submodules, each with their own constraint
files (detailing pin locations etc) in to a top level module? Ideally I
don't want to connect through all the signals through the top level module.
Why do I want to do this? - Because I am trying to make use of some modules
already written for a particular Xilinx development board (Microblaze and
multimedia XC2V2000). For example, there is a Clock generator module
(CLOCKGEN.V and CLOCKGEN.UCF). The constraint file contains the pin
locations of input clocks etc. In my top level module, I want to ignore
these connections, and just use the output of "CLOCKGEN.V".
Does anyone know how I might do this? Should I use a black-box
instantiation? (and if so... how? without having to specify the inputs to
"CLOCKGEN.V" that I want to know nothing about in the top-level module?)
(I am using Verilog).
With best regards
PETER MASH
Is there any way I can implement submodules, each with their own constraint
files (detailing pin locations etc) in to a top level module? Ideally I
don't want to connect through all the signals through the top level module.
Why do I want to do this? - Because I am trying to make use of some modules
already written for a particular Xilinx development board (Microblaze and
multimedia XC2V2000). For example, there is a Clock generator module
(CLOCKGEN.V and CLOCKGEN.UCF). The constraint file contains the pin
locations of input clocks etc. In my top level module, I want to ignore
these connections, and just use the output of "CLOCKGEN.V".
Does anyone know how I might do this? Should I use a black-box
instantiation? (and if so... how? without having to specify the inputs to
"CLOCKGEN.V" that I want to know nothing about in the top-level module?)
(I am using Verilog).
With best regards
PETER MASH