Implementing JK Flipflop in Verilog

[Atinesh S]

I'm trying to implement simple JK Flipflop in Verilog (Modelsim). But I'm getting the following error

The generate if condition must be a constant expression.
Here is the code which I'm using

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
if(J==0 & K==1)
begin
assign Q = 0;
end
else if(J==1 & K==0)
begin
assign Q = 1;
end
else if(J==1 & K==1)
begin
assign Q = ~Q;
end
endmodule
Can someone help me

 

[Galina Szakacs]

On 9/6/2015 12:53 AM, Atinesh S wrote:

I'm trying to implement simple JK Flipflop in Verilog (Modelsim). But I'm getting the following error

The generate if condition must be a constant expression.
Here is the code which I'm using

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
if(J==0 & K==1)
begin
assign Q = 0;
end
else if(J==1 & K==0)
begin
assign Q = 1;
end
else if(J==1 & K==1)
begin
assign Q = ~Q;
end
endmodule
Can someone help me

It looks like Modelsim is interpreting your "if" statements
as a "generate if" because they are not in a process. For
a flip-flop, you should have a process triggered on a clock
edge like:

always @ (posedge clk)
begin
if (J == 1 & K == 0)
. . .
end

Also you don't want to use "assign" inside a process, because
in this context it doesn't do what you think it does. Instead
Q should be a reg type instead of a wire:

output reg Q;

and assignments to Q in the body of the clocked process should
use a non-blocking assignment:

Q <= ~Q;

I assume you're just starting to learn Verilog. A good text
book with examples would be a help.

--
Gabor

 

[Nikolaos Kavvadias]

I think you haven't understood basic Verilog concepts such as what the concurrent assign is and does and the use of the initial and always blocks for sequential descriptions (careful! not sequential circuits!)

So here it is.

Excerpts from my Verilog HDL teaching materials: http://www.nkavvadias.com/courses/verilog/verilog_lecture_03.pdf (slides 17 to 18).

[FUN: Too bad Greek does not use a Latin script... But hey! Latin does use a Greek script. Latin is based on the Euboean variant of Greek alphabet. Just too many Greek alphabet variants around in the 6th century BC to pick up from I guess. Greeks stuck with the Athenian variant, everyone else got the Cymean one, essentially the variant from the island of Euboea.]

There you can find an implementation for a JK flip-flop as I used for teaching. Plus there is a ZIP file with the source code for the aforementioned lecture #03 on introductory Verilog HDL: http://www.nkavvadias.com/courses/verilog/verilog-code-03.zip

Best regards
Nikolaos Kavvadias