Implementing a reliable counter inside SDRAM memory mapped d

[valentin tihomirov]

The idea is to read a stream of words from a single address location. This
demands a mechanism to recognoze that a read cycle has finished. Is it
possible? As far as I understand, SDRAM is an asynchronous device. However,
4-way handshaking is not used, so it is not possible to mark the end of
transfer. Thanks.

 

[rickman]

valentin tihomirov wrote:

The idea is to read a stream of words from a single address location. This
demands a mechanism to recognoze that a read cycle has finished. Is it
possible? As far as I understand, SDRAM is an asynchronous device. However,
4-way handshaking is not used, so it is not possible to mark the end of
transfer. Thanks.

No, SDRAM *is* synchronous, hence the name SDRAM, "Synchronous DRAM".
Every cycle on the SDRAM bus is determined by the state of the five chip
wide control signals plus the byte specific DQM signal. To find the end
of a cycle, I think you only need to consider the chip wide signals
since the DQM only controls the enable for a transfer and does not
change the FSM.

To make this work you will need to either know exactly how your
controller operates, or you will need to study the SDRAM data sheets and
model the FSM of the SDRAM. It should be simpler to model the
controller since it is not likely to use every feature of the SDRAM.
But you may not have enough detail to know what it does and does not
use. Modeling the SDRAM will take a lot of reading to make sure you
have not missed anything, but it will work with all controllers. So
either approach has its problems.

--

Rick "rickman" Collins

rick.collins@XYarius.com
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[Tim Wescott]

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c2fodt$1t9i88$1@ID-212430.news.uni-berlin.de...

The idea is to read a stream of words from a single address location. This
demands a mechanism to recognoze that a read cycle has finished. Is it
possible? As far as I understand, SDRAM is an asynchronous device.
However,
4-way handshaking is not used, so it is not possible to mark the end of
transfer. Thanks.

It's really not obvious what you're trying to accomplish, but the 'S' in
SDRAM stands for "Synchronous". "Syncronous Dynamic Random Access Memory",
to be complete.

SDRAM needs a clock, and all transfers in and out of the device are
commanded from the controller and synchronized from the clock. When you do
burst reads/writes there is an internal counter in the chip that keeps
track.