IMPLEMENTING 32-BIT ALU WITH OVERFLOW DETECTION

  • Thread starter chibiks@googlemail.com
  • Start date
C

chibiks@googlemail.com

Guest
Hi all,

I am trying to implement a very simple 32-bit ALU capable of overflow
detection. Hence if the result of any computation (especially addition
and subtraction) results in a value > X'FFFFFFFF', then the system
should halt, freeze or a similar behaviour. Here is my code fragment
but it currently doesnt give expected behaviour - any suggestions
please?

LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_arith.ALL;



-- The ALU unit

ENTITY ALU_32 IS
PORT (a,b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
opcode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));

END ENTITY ALU_32;


ARCHITECTURE complex of ALU_32 is
signal undbit : bit;
signal overbit : bit;
BEGIN

-- Process is entered whenever the value of a, b or opcode changes
PROCESS(a,b,opcode)
VARIABLE alu_result : INTEGER; -- declares alu_result for result;
to be used within PROCESS only


BEGIN

CASE opcode is
--When addition
WHEN "001000" =>
alu_result:= CONV_INTEGER(a) + CONV_INTEGER(b); -- get the decimal
value of addition of a + b

--check for positive overflow
IF (alu_result > 31) THEN
overbit <= '1'; -- ALU does nothing
ELSE
overbit <= '0';
-- legal addition, it takes place
result <= CONV_STD_LOGIC_VECTOR(alu_result,32);
END IF;
-- check for negative overflow
IF (alu_result< -32) THEN
undbit <= '1'; -- ALU does nothing
ELSE
undbit <= '0';
-- legal negative addition, it takes place
result <= CONV_STD_LOGIC_VECTOR(alu_result,32);
END IF;
 
On 18 Jan 2007 15:25:12 -0800, "chibiks@googlemail.com"
<chibiks@googlemail.com> wrote:

Here is my code fragment
but it currently doesnt give expected behaviour - any suggestions
please?
This is comp.lang.verilog!

VARIABLE alu_result : INTEGER; -- declares alu_result for result;
....
--check for positive overflow
IF (alu_result > 31) THEN
overbit <= '1'; -- ALU does nothing
This doesn't check for 32-bit overflow - it just checks whether your
result is greater than 31. Try this with a pencil and paper to make
sure that you understand what underflow and overflow are. You could
start with, for example, 4-bit integers. The simple way to do this is
with a 5-bit adder/subtractor, though you can also do it by looking at
datflow in and out of the top bit.

/PJ
 
To get a better understanding of overflow, check out the following web
site.

http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Op_Ar2.htm

David Walker

Paul Jansen wrote:
On 18 Jan 2007 15:25:12 -0800, "chibiks@googlemail.com"
chibiks@googlemail.com> wrote:

Here is my code fragment
but it currently doesnt give expected behaviour - any suggestions
please?

This is comp.lang.verilog!

VARIABLE alu_result : INTEGER; -- declares alu_result for result;
....
--check for positive overflow
IF (alu_result > 31) THEN
overbit <= '1'; -- ALU does nothing

This doesn't check for 32-bit overflow - it just checks whether your
result is greater than 31. Try this with a pencil and paper to make
sure that you understand what underflow and overflow are. You could
start with, for example, 4-bit integers. The simple way to do this is
with a 5-bit adder/subtractor, though you can also do it by looking at
datflow in and out of the top bit.

/PJ
 

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