Implementation of Modbus Slave using only FPGA, without any

[Swapnil Patil]

Hello Folks,

I wanted to Implement Modbus Slave protocol with the use of only FPGA, without use of any external or internal softcore,Hardcore.

Currently i have successfully Implemented Modbus Master protcol, Now I am Looking forward to bulit Modbus Slave as well.

For Implementation Of Modbus Slave I am currently using Spartan6 FPGA and ISE 14.7 for For coding In VHDl.

I want some help to know how should I start with Implementation,Coding n all.
If possible share any document links as well.

Again I don't want to use any softcore so please suggest answers related to given FPGA only, Thanks.

 

On Thursday, March 14, 2019 at 1:38:31 AM UTC-4, Swapnil Patil wrote:

Hello Folks,

I wanted to Implement Modbus Slave protocol with the use of only FPGA, without use of any external or internal softcore,Hardcore.

Currently i have successfully Implemented Modbus Master protcol, Now I am Looking forward to bulit Modbus Slave as well.

For Implementation Of Modbus Slave I am currently using Spartan6 FPGA and ISE 14.7 for For coding In VHDl.

I want some help to know how should I start with Implementation,Coding n all.
If possible share any document links as well.

Again I don't want to use any softcore so please suggest answers related to given FPGA only, Thanks.

I don't understand your problem. If you have implemented a Modbus master, it would seem that you should understand it well enough to implement the slave as well.

Do you have any specific questions?

Rick C.

 

[Swapnil Patil]

I never designed slave before i have worked on master parts mostly.
While designing for modbus slave which parameters should i should take into accounts.
If somebody can explain the FSM flow? it would be great help.
Thanks.

 

On Thursday, March 14, 2019 at 2:51:46 AM UTC-4, Swapnil Patil wrote:

I never designed slave before i have worked on master parts mostly.
While designing for modbus slave which parameters should i should take into accounts.
If somebody can explain the FSM flow? it would be great help.
Thanks.

How does the master work?

Rick C.

 

[Swapnil Patil]

On Thursday, March 14, 2019 at 1:44:36 PM UTC+5:30, gnuarm.del...@gmail.com wrote:

On Thursday, March 14, 2019 at 2:51:46 AM UTC-4, Swapnil Patil wrote:
I never designed slave before i have worked on master parts mostly.
While designing for modbus slave which parameters should i should take into accounts.
If somebody can explain the FSM flow? it would be great help.
Thanks.

How does the master work?

Rick C.

First it calculates CRC and stores in register. Then i wrote FSM accordingly it first send slave address then function code, Data and at last CRC calculated. i used r232 UART communication hence i send all the packets via UART communication at 19200 baud rate.
according to clock i adjusted my t1.5 and t3.5 timer to match timing in accordance modbus slandered protocol.
i checked output using slave simulator it works.

 

[Andy Bennet]

On 14/03/2019 08:47, Swapnil Patil wrote:

On Thursday, March 14, 2019 at 1:44:36 PM UTC+5:30, gnuarm.del...@gmail.com wrote:
On Thursday, March 14, 2019 at 2:51:46 AM UTC-4, Swapnil Patil wrote:
I never designed slave before i have worked on master parts mostly.
While designing for modbus slave which parameters should i should take into accounts.
If somebody can explain the FSM flow? it would be great help.
Thanks.

How does the master work?

Rick C.

First it calculates CRC and stores in register. Then i wrote FSM accordingly it first send slave address then function code, Data and at last CRC calculated. i used r232 UART communication hence i send all the packets via UART communication at 19200 baud rate.
according to clock i adjusted my t1.5 and t3.5 timer to match timing in accordance modbus slandered protocol.
i checked output using slave simulator it works.

As you don't appear to understand it at all, I'm guessing you copied the
Modbus master design from elsewhere as well.
How does the slave simulator work? You might find a few clues in that.

 

[Swapnil Patil]

Okay First thing I haven't copied it. I wrote it myself. I know how master part works and I just explained how I designed it.
And Secondly don't put posts just to show off, if you really want help give the solution if you really that smart enough..!!

 

On Thursday, March 14, 2019 at 4:47:35 AM UTC-4, Swapnil Patil wrote:

On Thursday, March 14, 2019 at 1:44:36 PM UTC+5:30, gnuarm.del...@gmail.com wrote:
On Thursday, March 14, 2019 at 2:51:46 AM UTC-4, Swapnil Patil wrote:
I never designed slave before i have worked on master parts mostly.
While designing for modbus slave which parameters should i should take into accounts.
If somebody can explain the FSM flow? it would be great help.
Thanks.

How does the master work?

Rick C.

First it calculates CRC and stores in register. Then i wrote FSM accordingly it first send slave address then function code, Data and at last CRC calculated. i used r232 UART communication hence i send all the packets via UART communication at 19200 baud rate.
according to clock i adjusted my t1.5 and t3.5 timer to match timing in accordance modbus slandered protocol.
i checked output using slave simulator it works.

Based on that info I'm pretty sure I could design a slave. I'm not sure what you mean by t1.5 and t3.5, but otherwise it seems pretty simple. What don't you understand about designing the slave?

One of the things I learned in computer programming was a good start to organizing your program is to determine what data structures your program will need. HDL is not different. The data structures will be the registers holding the data. You will need a UART receiver with a receiving register but might not need the holding register since I expect all the other registers can always be available when the data comes in.

Then you will need an address register or... if the address is only to select this slave and not to select destinations in the slave you can use a state machine to recognize a match to the address. Likewise the function code can be held in a register or matched with a state machine. Finally you will need a register for the data and the register to calculate the CRC of the received message which will be matched to the incoming CRC when it arrives. I suppose you should also have a state machine to organize the overall operation of these circuits.

What is not clear to me is what happens to the data when it is received. You will need an output to indicate there is a valid output and possibly a hand shake back saying the data was accepted.

Does that make sense?

Rick C.

 

[KJ]

I suspect the answer will be 'No' but never discount the obvious, so don't be offended: While implementing the master did you write a test bench to verify it? After all, the test bench for the master for any protocol is (or could be) the slave, and vice versa. Even if that test bench is not synthesizable it gives you a starting point and reframes the query into how to convert a test bench into something that can be synthesized.

Kevin Jennings

 

torsdag den 14. marts 2019 kl. 15.14.49 UTC+1 skrev Swapnil Patil:

Okay First thing I haven't copied it. I wrote it myself. I know how master part works and I just explained how I designed it.
And Secondly don't put posts just to show off, if you really want help give the solution if you really that smart enough..!!

if you know how the master works you also know how the slave works