Implement filter in verilog

[Marvin L]

Dear all verilog seniors.

I am doing a small school project to design an image filter in verilog.

It can be summarized in this picture:
http://imageshack.com/a/img924/2851/Rt9ZI6.png

I have the following filter equation


h[j] = A*h[i-1][j-1] + B*h[j-1] + C*h[i+1][j-1] + D*h[i-1][j] + E*h[j] + F*h[i+1][j] + G*h[i-1][j+1] + H*h[j+1] + I*h[i+1][j+1]


However, I have no prior knowledge in RTL/verilog.


How should I proceed ?

 

[rickman]

On 3/8/2016 6:36 PM, Marvin L wrote:

Dear all verilog seniors.

I am doing a small school project to design an image filter in verilog.

It can be summarized in this picture:
http://imageshack.com/a/img924/2851/Rt9ZI6.png

I have the following filter equation


h[j] = A*h[i-1][j-1] + B*h[j-1] + C*h[i+1][j-1] + D*h[i-1][j] + E*h[j] + F*h[i+1][j] + G*h[i-1][j+1] + H*h[j+1] + I*h[i+1][j+1]


However, I have no prior knowledge in RTL/verilog.


How should I proceed ?

There are more than one ways to skin a cat and they depend on your
purpose and requirements. If this is just for simulation and you don't
need to synthesize it, you would code it much like you have written it
above, but using the syntax for Verilog.

If you need to synthesize this code you need to consider clock cycles.
I assume you will be doing this over a range of i and j? If so you will
need to iterate over those two variables either in time or in space. By
space, I mean parallel hardware. So if you have the time to use one
instance of hardware to calculate the value of a single cell (h[j])
and reuse that for multiple values of i and j you will code it using
counters that are synthesized. If you don't have the time to iterate
through the cells you will need parallel hardware which means a counter
is used to infer multiple instances of the same hardware. This will use
a *lot* of space in your device. You can iterate in space with one
variable and in time with the other variable too.

If you are pressed for resources in your device and you have all the
time in the world, the multiple operations to calculate one cell can be
done in a time loop as well.

Any of that make sense? If you don't know any of the syntax for
Verilog, you need to get a good book and read and program up some
examples. An image filter is not the best project to learn an HDL on.

--

Rick

 

[GaborSzakacs]

Marvin L wrote:

Dear all verilog seniors.

I am doing a small school project to design an image filter in verilog.

It can be summarized in this picture:
http://imageshack.com/a/img924/2851/Rt9ZI6.png

I have the following filter equation


h[j] = A*h[i-1][j-1] + B*h[j-1] + C*h[i+1][j-1] + D*h[i-1][j] + E*h[j] + F*h[i+1][j] + G*h[i-1][j+1] + H*h[j+1] + I*h[i+1][j+1]


However, I have no prior knowledge in RTL/verilog.


How should I proceed ?

How you go about this for hardware mostly depends on how you get the
image data. If you already have the whole image stored in your
hardware, for example in block RAM of an FPGA, then you can
simply loop through the image (sequentially if you don't have
a very large device). If you need to work on live image data
from a camera in real time, then you would probably use a
different approach using at least two (three may be easier)
line buffers and another 3 x 3 buffer for the kernel. Line
buffers can be implemented in block RAM, but the kernel would
be in loose flip-flops so you access the entire 3 x 3 array
in a single clock cycle. You might want to look for examples
of a Sobel filter to see if there are some useful coding
examples available.

--
Gabor

 

[Prasad Pandit]

On Tuesday, March 8, 2016 at 3:36:10 PM UTC-8, Marvin L wrote:

Dear all verilog seniors.

I am doing a small school project to design an image filter in verilog.

It can be summarized in this picture:
http://imageshack.com/a/img924/2851/Rt9ZI6.png

I have the following filter equation


h[j] = A*h[i-1][j-1] + B*h[j-1] + C*h[i+1][j-1] + D*h[i-1][j] + E*h[j] + F*h[i+1][j] + G*h[i-1][j+1] + H*h[j+1] + I*h[i+1][j+1]


However, I have no prior knowledge in RTL/verilog.


How should I proceed ?

Hi,

I think unrolling the logic with pipeline will help to produce small and efficient design for above equation. Think of state machines. since have so many multipliers and adders in one big combinatorial cloud will slow down the whole design. Reusing some parts of it will make it a lot faster and efficient.