Impact of voltage variations on timings for an FPGA

[jean-francois hasson]

Hi,

I have read the article about slack and margins written by Austin Lesea and
I am anxious to have more information concerning "any ripple or noise
detracts directly from the speed of the part. 200 mV peak-to-peak of noise
and ripple on the internal core power supply of a 1.5 volt part results in a
significant slowdown". How big is the impact of the ripple on the timings. I
believe the converters on the board I have can provide 50mV peak-to-peak of
ripple/noise. Will my timing margins degrade ? Any type of information will
be welcome.

Thanks,

JF

 

[Austin Lesea]

JF,

As long as the voltage never goes below the min (1.425V in this case),
noise included, all timing will be met (we guard-band the speeds files
and do all testing at hot, and low Vcc).

If, however, the noise takes you below 1.425V, then you degrade the timing.

Additionally, noise adds jitter, which should be characterized
(measured) which also reduces the slack.

Austin

jean-francois hasson wrote:

Hi,

I have read the article about slack and margins written by Austin Lesea and
I am anxious to have more information concerning "any ripple or noise
detracts directly from the speed of the part. 200 mV peak-to-peak of noise
and ripple on the internal core power supply of a 1.5 volt part results in a
significant slowdown". How big is the impact of the ripple on the timings. I
believe the converters on the board I have can provide 50mV peak-to-peak of
ripple/noise. Will my timing margins degrade ? Any type of information will
be welcome.

Thanks,

JF

 

[Paul Leventis (at home)]

Hi Jean,

For Altera's FPGAs, the timing produced by Quartus will take into any
internal voltage drops. So provided that your external Vdd does not drop
below the minimum value spec'ed in the data sheet (for example, 1.425 V for
Stratix/GX/Cyclone vs. 1.5V nominal), your timing report will be valid.

Regards,

Paul Leventis
Altera Corp.

"jean-francois hasson" <jfhasson@club-internet.fr> wrote in message
news:40082283$0$6968$7a628cd7@news.club-internet.fr...

Hi,

I have read the article about slack and margins written by Austin Lesea
and
I am anxious to have more information concerning "any ripple or noise
detracts directly from the speed of the part. 200 mV peak-to-peak of noise
and ripple on the internal core power supply of a 1.5 volt part results in
a
significant slowdown". How big is the impact of the ripple on the timings.
I
believe the converters on the board I have can provide 50mV peak-to-peak
of
ripple/noise. Will my timing margins degrade ? Any type of information
will
be welcome.

Thanks,

JF