I'm begging for help. VerilogA (cadence) 6lines

[ountalaga]

Hi, I'm modeling a VCSEL on VerilogA and my code does not work. When I try to simulate "N" I get a flat line. I wrote the code in Matlab before writing it in VerilogA. Thanks a million.

Here is the code of that part in Matlab:

For i=1:20
XXs = S*k;
XXn = N/zn;

qzni = q*zn/Etai;
ddXn = (Ira-Ioff)-XXn*qzni/Taon - (q/(Etai*k))*Go*(zn*XXn-No)*Xs/(1+(epsilon*XXs/k));
ddXs = -XXs + k*Taop*Beta*zn*XXn/Taon + Taop*Go*(zn*XXn-No)*XXs/(1+(epsilon*XXs/k));

XXn = Xn + ddXn;
XXs = Xs + ddXs;
XXn = XXn*0.5*(1+tanh(XXn*10e20)); % XXn [0 to infinity
XXs = XXs*0.5*(1+tanh(XXs*10e20)); % XXs [0 to infinity

S = XXs/k;
N = XXn*zn;
end


My VerilogA code:

electrical S,N;
real XXs,XXn,qzni,ddXn,ddXs,nXn,nXs;

XXs = V(S,refnode)*k;
XXn = V(N,refnode)/zn;
qzni = q*zn/Etai;

ddXn = (I(anode)-Ioff)-XXn*qzni/Taon - (q/(Etai*k))*Go*(zn*XXn-No)*XXs/(1+(epsilon*XXs/k));
ddXs = -XXs + k*Taop*Beta*zn*XXn/Taon + Taop*Go*(zn*XXn-No)*XXs/(1+(epsilon*XXs/k));

nXn = (XXn+ddXn)*0.5*(1+tanh((XXn+ddXn)*10e30));
nXs = (XXs+ddXs)*0.5*(1+tanh((XXs+ddXs)*10e30));

I(S,refnode) <+ -ddt(V(S,refnode))+nXs/k;
I(N,refnode) <+ -ddt(V(N,refnode))+nXn*zn;