"Illegal output or inout port connection for "port"

[valtih1978]

I see this problem ubiquitous -- nobody can figure out what this
intelligent message means. I also cannot figure out the solutions in the
forums because everybody posts is whole project. I have localized the
error. Where is it?

module CPU (inout
//reg
//wire

[7:0] data_bus);

//assign data_bus = 1 ? 0 : 8'bzzzz_zzzz;

endmodule

module SIMULATE_CPU;

reg [7:0] data_bus;

CPU cpu (data_bus );

reg clk;

always @(posedge clk) begin
data_bus <= 1;
end

endmodule

# ** Error: (vsim-3053) tb.v(15): Illegal output or inout port
connection for "port 'data_bus'".
# Region: /SIMULATE_CPU/cpu

Did Verilog developers introduced wire/reg separation for fun?

 

[Robert Miles]

On 2/27/2013 2:39 PM, valtih1978 wrote:

I see this problem ubiquitous -- nobody can figure out what this
intelligent message means. I also cannot figure out the solutions in
the forums because everybody posts is whole project. I have localized
the error. Where is it?

module CPU (inout
//reg
//wire

[7:0] data_bus);

//assign data_bus = 1 ? 0 : 8'bzzzz_zzzz;

endmodule

module SIMULATE_CPU;

reg [7:0] data_bus;

CPU cpu (data_bus );

reg clk;

always @(posedge clk) begin
data_bus <= 1;
end

endmodule

# ** Error: (vsim-3053) tb.v(15): Illegal output or inout port
connection for "port 'data_bus'".
# Region: /SIMULATE_CPU/cpu

Did Verilog developers introduced wire/reg separation for fun?
The Verilog compilers I remember didn't have automatic connections of a

scalar
signal to a multi-bit register. However, that was about 11 years ago.

Wires were for conducting any changes on a signal.

Registers were for letting the output signal change only on the
specified edge
of the clock signal.

 

[valtih1978]

Thanks. This answers my second part of the question. I still want to
understand what is wrong with illegal I/O port 'data_bus'. I have
reduced my demo to

module CPU (output
[7:0] data_bus);

endmodule

module SIMULATE_CPU;

reg [7:0] data_bus;

CPU cpu (data_bus ); // illegal port connection

endmodule


but still getting the error.

 

[valtih1978]

Ok, I have got the answer

http://stackoverflow.com/questions/12394040/having-trouble-with-verilog-inout-wires

The workaround is to have the tri-state port as bus and drive it through
an extra declared reg.

 

[valtih1978]

I mean we are forced to have the tri-state port as wire and declare
extra reg for driving it.