illegal condition on timing check terminal.

P

paz

Guest
I'm getting this error when trying to compile my verilog file:.


$setup(SDA, posedge SCL &&& (operation == `read && state !=
`waitingAck), 1600);
|

ncvlog: *E,TCBEXP
(/vobs/vb_msc7130/blocks/i2c/testbench/modules_v/e2prom.v,129|74):
illegal condition on timing check terminal.


I guess the reason for fail is the "&&" in the condition.
Am I right?
Do you have any susggestion how to fix it?



Thanks,
Pazia
 
Hi,

I guess the reason for fail is the "&&" in the condition.
Am I right?
Click to expand...
I believe so.

Do you have any susggestion how to fix it?
Click to expand...
Model the and with an extra wire/reg and use it in the $setup check,
such as:

assign extra_tcheck_w = (operation == `read && state !=
`waitingAck);

(You may also use and() instantiation to remain 100% structural, some
back end tools don't like assign etc.).

$setup(SDA, posedge SCL &&& extra_tcheck_w, 1600);
Click to expand...

Does that help?

Ajeetha, CVC
www.noveldv.com

paz wrote:
I'm getting this error when trying to compile my verilog file:.


$setup(SDA, posedge SCL &&& (operation == `read && state !=
`waitingAck), 1600);
|

ncvlog: *E,TCBEXP
(/vobs/vb_msc7130/blocks/i2c/testbench/modules_v/e2prom.v,129|74):
illegal condition on timing check terminal.





Thanks,
Pazia
Click to expand...
 
When you get an error message that doesn't make sense, try using
"nchelp". For example,

nchelp ncvlog tcbexp
nchelp: 05.83-p002: (c) Copyright 1995-2006 Cadence Design Systems,
Click to expand...
Inc.
ncvlog/tcbexp =
Only simple scalar conditions with a single identifier are
allowed
on timing check terminals like
==, !=, ===, !===, ~

David Walker

paz wrote:
I'm getting this error when trying to compile my verilog file:.


$setup(SDA, posedge SCL &&& (operation == `read && state !=
`waitingAck), 1600);
|

ncvlog: *E,TCBEXP
(/vobs/vb_msc7130/blocks/i2c/testbench/modules_v/e2prom.v,129|74):
illegal condition on timing check terminal.


I guess the reason for fail is the "&&" in the condition.
Am I right?
Do you have any susggestion how to fix it?



Thanks,
Pazia
Click to expand...
 
yes, it does help. Thank-you!


Ajeetha (www.noveldv.com) wrote:
Hi,

I guess the reason for fail is the "&&" in the condition.
Am I right?

I believe so.

Do you have any susggestion how to fix it?


Model the and with an extra wire/reg and use it in the $setup check,
such as:

assign extra_tcheck_w = (operation == `read && state !=
`waitingAck);

(You may also use and() instantiation to remain 100% structural, some
back end tools don't like assign etc.).

$setup(SDA, posedge SCL &&& extra_tcheck_w, 1600);


Does that help?

Ajeetha, CVC
www.noveldv.com

paz wrote:
I'm getting this error when trying to compile my verilog file:.


$setup(SDA, posedge SCL &&& (operation == `read && state !=
`waitingAck), 1600);
|

ncvlog: *E,TCBEXP
(/vobs/vb_msc7130/blocks/i2c/testbench/modules_v/e2prom.v,129|74):
illegal condition on timing check terminal.





Thanks,
Pazia
Click to expand...
 
I know this feature, this is very usefull. Thanks!

dbwalker0min@gmail.com wrote:
When you get an error message that doesn't make sense, try using
"nchelp". For example,

nchelp ncvlog tcbexp
nchelp: 05.83-p002: (c) Copyright 1995-2006 Cadence Design Systems,
Inc.
ncvlog/tcbexp =
Only simple scalar conditions with a single identifier are
allowed
on timing check terminals like
==, !=, ===, !===, ~

David Walker

paz wrote:
I'm getting this error when trying to compile my verilog file:.


$setup(SDA, posedge SCL &&& (operation == `read && state !=
`waitingAck), 1600);
|

ncvlog: *E,TCBEXP
(/vobs/vb_msc7130/blocks/i2c/testbench/modules_v/e2prom.v,129|74):
illegal condition on timing check terminal.


I guess the reason for fail is the "&&" in the condition.
Am I right?
Do you have any susggestion how to fix it?



Thanks,
Pazia
Click to expand...
 
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