iir filter

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francesco_pincio

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Hello!
I'm new in the forum and just done an FPGA university course, very ver
small...we have only turned on/off led with finite state machine and s
on...now i'm tryng to develope an IIR filter with XSA50 board form Xes
with spartanIIe50 fpga. FIlter kernel is just a 2 pole system with a zer
in 0, i would do a bandpass with changable passaband with pushbuttons;
've idealized that main structure of the program would be a module with
counter for generating clock for the ADC/DAC, a module that pass thi
samples in the filtern kernel, the filter kernel iir itself and a modul
that passes filtererd samples to DAC; mainly i have 2 problems:

1) i can do only operation with radix-2 coefficient, so i can use only 1/2
1/4 an so on. i don't understand how to pass a float value and multiply it

2)do i need a ram to store at least y[n-2] sample?

I know myquestions sounds stupid, maybe i have not a good idea of what
have to do, if you could illuminate me on this...

best regards

francesco



---------------------------------------
Posted through http://www.FPGARelated.com
 
1) i can do only operation with radix-2 coefficient, so i can use onl
1/2,
1/4 an so on. i don't understand how to pass a float value and multipl
it
Click to expand...

You probably don't need floating point. Floating-point is difficult o
FPGAs.
Imagine your ADC data as between -1 and +1. Then, when you multiply, th
result is still between -1 and +1. After additions, scale your data so i
is again between -1 and +1.

There is a difficulty with IIR filters in digital hardware, which i
arithmetic saturation. You will need to do simulations to prove that eithe
it doesn't happen or that you detect and mitigate it.

2)do i need a ram to store at least y[n-2] sample?
Click to expand...
Unless the number and size of samples is very large, it could be done wit
registers (flip/flops). You need to sketch out how the data flows throug
the arithmetic elements.



---------------------------------------
Posted through http://www.FPGARelated.com
 
On Wed, 02 Mar 2011 08:37:35 -0600, francesco_pincio wrote:

Hello!
I'm new in the forum and just done an FPGA university course, very very
small...we have only turned on/off led with finite state machine and so
on...now i'm tryng to develope an IIR filter with XSA50 board form Xess
with spartanIIe50 fpga. FIlter kernel is just a 2 pole system with a
zero in 0, i would do a bandpass with changable passaband with
pushbuttons; i 've idealized that main structure of the program would be
a module with a counter for generating clock for the ADC/DAC, a module
that pass this samples in the filtern kernel, the filter kernel iir
itself and a module that passes filtererd samples to DAC; mainly i have
2 problems:

1) i can do only operation with radix-2 coefficient, so i can use only
1/2, 1/4 an so on. i don't understand how to pass a float value and
multiply it
Click to expand...
Who needs floating point? You can do this all with fixed point
arithmetic. Let your coefficients range from -1 to 1, or 0 to 2, or
whatever you need, then implement your filter. In an HDL, this is a
matter of doing your multiplication, and picking the leftmost (or nearly
leftmost) bits out of the answer, instead of the rightmost.

sample?
Click to expand...
Are you trying to do this in batch mode, or continuous? If it's
continuous, you should only need to keep two filter states.

You will find that you need to keep more precision on your filter states
than you have on your incoming (and probably outgoing) data.

This is not a subject that can be done justice to in a newsgroup posting,
and everyone and his sister wants to know. Do a web search on "IIR
Filter for FPGA" and you should find at least one tutorial.

--
http://www.wescottdesign.com
 
On Wed, 02 Mar 2011 08:37:35 -0600, francesco_pincio wrote:

Hello!
I'm new in the forum and just done an FPGA university course, very very
small...we have only turned on/off led with finite state machine and so
on...now i'm tryng to develope an IIR filter with XSA50 board form Xess
with spartanIIe50 fpga. FIlter kernel is just a 2 pole system with a
zero in 0, i would do a bandpass with changable passaband with
pushbuttons; i 've idealized that main structure of the program woul
be
a module with a counter for generating clock for the ADC/DAC, a module
that pass this samples in the filtern kernel, the filter kernel iir
itself and a module that passes filtererd samples to DAC; mainly i have
2 problems:

1) i can do only operation with radix-2 coefficient, so i can use only
1/2, 1/4 an so on. i don't understand how to pass a float value and
multiply it

Who needs floating point? You can do this all with fixed point
arithmetic. Let your coefficients range from -1 to 1, or 0 to 2, or
whatever you need, then implement your filter. In an HDL, this is a
matter of doing your multiplication, and picking the leftmost (or nearly
leftmost) bits out of the answer, instead of the rightmost.

2)do i need a ram to store at least y[n-2] sample?

Are you trying to do this in batch mode, or continuous? If it's
continuous, you should only need to keep two filter states.

You will find that you need to keep more precision on your filter states
than you have on your incoming (and probably outgoing) data.

This is not a subject that can be done justice to in a newsgroup posting

and everyone and his sister wants to know. Do a web search on "IIR
Filter for FPGA" and you should find at least one tutorial.

--
http://www.wescottdesign.com
Click to expand...

Excuse me for the time, but I'm waiting for a mail from the forum saying m
anyone has replyed to my post...i want to thank for the help and the tip
that you have given me. Now i try to restudy verilog concepts and appl
your tips.

---------------------------------------
Posted through http://www.FPGARelated.com
 
On 03/02/2011 08:26 AM, Tim Wescott wrote:
On Wed, 02 Mar 2011 08:37:35 -0600, francesco_pincio wrote:

Hello!
I'm new in the forum and just done an FPGA university course, very very
small...we have only turned on/off led with finite state machine and so
on...now i'm tryng to develope an IIR filter with XSA50 board form Xess
with spartanIIe50 fpga. FIlter kernel is just a 2 pole system with a
zero in 0, i would do a bandpass with changable passaband with
pushbuttons; i 've idealized that main structure of the program would be
a module with a counter for generating clock for the ADC/DAC, a module
that pass this samples in the filtern kernel, the filter kernel iir
itself and a module that passes filtererd samples to DAC; mainly i have
2 problems:

1) i can do only operation with radix-2 coefficient, so i can use only
1/2, 1/4 an so on. i don't understand how to pass a float value and
multiply it

Who needs floating point? You can do this all with fixed point
arithmetic. Let your coefficients range from -1 to 1, or 0 to 2, or
whatever you need, then implement your filter. In an HDL, this is a
matter of doing your multiplication, and picking the leftmost (or nearly
leftmost) bits out of the answer, instead of the rightmost.

2)do i need a ram to store at least y[n-2] sample?

Are you trying to do this in batch mode, or continuous? If it's
continuous, you should only need to keep two filter states.

You will find that you need to keep more precision on your filter states
than you have on your incoming (and probably outgoing) data.

This is not a subject that can be done justice to in a newsgroup posting,
and everyone and his sister wants to know. Do a web search on "IIR
Filter for FPGA" and you should find at least one tutorial.
Click to expand...
Dangit! I forgot my shameless plug!!!

The last chapter of my book, "Applied Control Theory for Embedded
Systems" shows how to implement fixed-point filters in C, and discusses
the issues of implementing fixed-point filters in general. There's no
HDL of any kind (which, in hindsight, I see I should have included).
But you may find it useful none the less.

http://www.wescottdesign.com/actfes/actfes.html
http://www.elsevier.com/wps/find/bookdescription.cws_home/707797/description#description

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
Hello, i'm returned, maybe with better knowledges in verilg... my desig
file is synthetizable and implementable. My question is how it is possibl
that a 8x8 multiplier occupy 60 SLICES, synthetized alone, and all th
entire system, with 3 bigger multiplier occupy only 13 SLICES??
if you would try to synthetize this file...maybe it is a big example fo
how a iir filter does not work...

What is wrong?

Best regards...

//ALL SYSTEM IN VERILOG
module multiplier_10x10(
out_dato,
x_1,
x_2//,
//clk
);

output [21:0] out_dato;
wire [21:0] out_dato;
input [10:0] x_1;
// input clk;
input [10:0] x_2;
// always @ (posedge clk) begin
assign out_dato = x_1*x_2;
// end
endmodule

module divisor_clock_codec( clk,
reset_in,
cinquanta_M,
venticinque_M,
dodiciecinque_M,
trepuntocentoventicinque_M,
quarantokappa_M);
// gen various clock for codec
input clk;
input reset_in;
output cinquanta_M;
output venticinque_M;
output dodiciecinque_M;
output trepuntocentoventicinque_M;
output quarantokappa_M;
reg [10:0] counter;
always @(posedge clk)
begin: COUNT_PLUS_ONE
counter <= counter+1;
end
assign cinquanta_M = clk;
assign venticinque_M = counter[1];
assign dodiciecinque_M = counter[2];
assign trepuntocentoventicinque_M = counter[3];
assign quarantokappa_M = counter[10];
endmodule

module sum11bit(
out_dato,
x_1,
x_2
);
input [10:0] x_1;
input [10:0] x_2;
output [10:0] out_dato;
assign out_dato=x_1+x_2;
endmodule

module sum22bit(
out_dato,
x_1,
x_2
);
input [21:0] x_1;
input [21:0] x_2;
output [21:0] out_dato;
assign out_dato=x_1+x_2;
endmodule

module binario_to_compl2_c(
par_in,
par_out
);

parameter WIDTH=11;
input [WIDTH-1:0] par_in;
output [WIDTH-1:0] par_out;
assign par_out=(~par_in)+1'd1;
endmodule

module ser_to_par( // converter serial-parallel
clk,
ser_in,
par_out
);
input clk;
input ser_in;
output [10:0] par_out;
reg [10:0] par_out;
reg indice_count=7'b0;
always @ (posedge clk)
begin : PILA_VALORI
if(indice_count<8) begin
par_out[indice_count]=ser_in;
indice_count<=indice_count+1;
end
else indice_count=7'b0;
end
endmodule

module par_to_ser( // converter parallel-serial
clk,
par_in,
ser_out
);
input clk;
input [21:0] par_in;
output ser_out;
reg indice_contat=16'b0;
reg ser_out;
always @ (posedge clk)
begin: SPILA_VALORI
if(indice_contat<16) begin
ser_out=par_in[indice_contat];
indice_contat<=indice_contat+1;
end
else indice_contat=16'b0;
end
endmodule

module filt_iir_lowpass(//filter kernel
clk,
alpha,
sample_in,
sample_out
);
input [10:0] alpha;
input clk;
input [10:0] sample_in;
output [21:0]sample_out;
wire [21:0] y_2_molt;
wire [21:0] y_1_molt;
//wire [15:0] x_1_molt;
wire [21:0] x_molt;
wire[21:0] y_tot;
reg [10:0] y_1;
reg [10:0] y_2;
//reg [7:0] x_1;
//reg [7:0] x_2;
multiplier_10x10 MOL1 (y_2_molt,y_2,8'd3);//,clk);
multiplier_10x10 MOL2(y_1_molt,y_1,alpha);//,clk);
multiplier_10x10 MOL3(x_molt,sample_in,8'd2);//,clk);
sum11bit SOM_Y(y_tot,y_1_molt,y_2_molt);
sum22bit SOM_FIN(sample_out,y_tot,x_molt);
always @(posedge clk)
begin
y_2=y_1;
y_1=sample_out;
end
endmodule

module total_sys(alpha, //implementazione moduli in intero sistema
clk_pad_in,
push_reset,
sdto_from_adc,
lrclk_to_dac,
mclk_to_dac,
sclk_to_dac,
sdti_to_dac);

input [10:0] alpha;
input clk_pad_in;
input push_reset;
input sdto_from_adc;
output lrclk_to_dac;
output mclk_to_dac;
output sclk_to_dac;
output sdti_to_dac;

wire [10:0] alpha_cin_compl2;
wire clock_global_to_all;
wire [10:0] dal_ser_par_al_filter_kernel;
wire [21:0] sample_da_serializ;

binario_to_compl2_c bin_to_2compl (.par_in(alpha[10:0]),
.par_out(alpha_cin_compl2[10:0]));

divisor_clock_codec clock_divisore (.clk(clk_pad_in),
.reset_in(push_reset),
.cinquanta_M(clock_global_to_all),
.dodiciecinque_M(mclk_to_dac),
.quarantokappa_M(lrclk_to_dac),
.trepuntocentoventicinque_M(sclk_to_dac),
.venticinque_M());

filt_iir_lowpass filter_kernel (.alpha(alpha_cin_compl2[10:0]),
.clk(clock_global_to_all),
.sample_in(dal_ser_par_al_filter_kernel[10:0]),
.sample_out(sample_da_serializ[21:0]));

par_to_ser par_to_ser_conv (.clk(clock_global_to_all),
.par_in(sample_da_serializ[21:0]),
.ser_out(sdti_to_dac));

ser_to_par ser_to_par_conv (.clk(clock_global_to_all),
.ser_in(sdto_from_adc),
.par_out(dal_ser_par_al_filter_kernel[10:0]));

endmodule

---------------------------------------
Posted through http://www.FPGARelated.com
 
On 4/19/2011 7:20 AM, francesco_pincio wrote:
Hello, i'm returned, maybe with better knowledges in verilg... my design
file is synthetizable and implementable. My question is how it is possible
that a 8x8 multiplier occupy 60 SLICES, synthetized alone, and all the
entire system, with 3 bigger multiplier occupy only 13 SLICES??
if you would try to synthetize this file...maybe it is a big example for
how a iir filter does not work...

What is wrong?
Click to expand...
You might be best off looking at the PaR report. It will indicate what
logic is being removed based on unused outputs.

How many multipliers utilized in the design using (from PaR summary)?
What device is this target for, I assume a Xilinx device since you are
using the SLICE terminology.

Chris Felton
 
You might be best off looking at the PaR report. It will indicate what
logic is being removed based on unused outputs.

How many multipliers utilized in the design using (from PaR summary)?
What device is this target for, I assume a Xilinx device since you are
using the SLICE terminology.

Chris Felton
Click to expand...
Hello Sir, yes i'm using Xilinx Spartan 2 con 50k gates on tq144packag
(x2s50-5tq144) on a Xess XSA-50 board:
I attach :

1)

Advanced HDL Synthesis Report

Macro Statistics
# Multipliers : 3
11x11-bit multiplier : 3
# Adders/Subtractors : 3
11-bit adder : 2
22-bit adder : 1
# Counters : 1
11-bit up counter : 1
# Registers : 27
Flip-Flops : 27


2) FROM PAR report seems no multiplier are removed...i don't understand

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:534 - The following XORCY(s) is/are demoted to LUTs becaus
there is
no MUXCY associated with them. Therefore, we cannot recognize th
standard
carry chain structure:
XORCY symbol "filter_kernel/MOL1/Mmult_out_dato_Madd_xor<1>" (output
signal=filter_kernel/y_2_molt<1>),
XORCY symbol "filter_kernel/MOL2/Mmult_out_dato_Madd9_xor<1>" (output
signal=filter_kernel/y_1_molt<1>),
XORCY symbol "filter_kernel/SOM_FIN/Madd_out_dato_xor<1>" (output
signal=sample_da_serializ<1>)
INFO:LIT:244 - All of the single ended outputs in this design are usin
slew
rate limited output drivers. The delay on speed critical single ende
outputs
can be dramatically reduced by designating them as fast outputs.

Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
11 Block(s) redundant

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC

Redundant Block(s):
TYPE BLOCK
LUT1 clock_divisore/Mcount_counter_cy<1>_rt
LUT1 clock_divisore/Mcount_counter_cy<2>_rt
LUT1 clock_divisore/Mcount_counter_cy<3>_rt
LUT1 clock_divisore/Mcount_counter_cy<4>_rt
LUT1 clock_divisore/Mcount_counter_cy<5>_rt
LUT1 clock_divisore/Mcount_counter_cy<6>_rt
LUT1 clock_divisore/Mcount_counter_cy<7>_rt
LUT1 clock_divisore/Mcount_counter_cy<8>_rt
LUT1 clock_divisore/Mcount_counter_cy<9>_rt
LUT1 clock_divisore/Mcount_counter_xor<10>_rt
INV ser_to_par_conv/indice_count_0_not00001_INV_0


---------------------------------------
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