ieee_proposed FPHDL in synthesis

Hi all,
Can somebody guide me that how can I use ieee_proposed for synthesis.
Can i make library ieee_proposed in Synplify-pro to be used for
synthesizing my VHDL's which uses this library?
David has told in some replies that he used Synplicity for the same.

 

[David Bishop]

vedpsingh@gmail.com wrote:

Hi all,
Can somebody guide me that how can I use ieee_proposed for synthesis.

Ok. I wrote these packages, and I use them all the time.

Can i make library ieee_proposed in Synplify-pro to be used for
synthesizing my VHDL's which uses this library?

After you add the code in Synplify_pro, right click on it and do a "set
library".

David has told in some replies that he used Synplicity for the same.

Yes I do. They work (with some minor fixes) almost everywhere BUT XST,
and they plan to fix that in the next major release.

 

David, You have mentioned in user guide(fixed_ug.pdf) that :

The files needed are ?fixed_generic_pkg.vhd?,
?fixed_generic_pkg_body.vhd?, and ?fixed_pkg.vhd?. These
packages have been designed for use in VHDL-2005, where they will be
part of the new IEEE library. However, a compatibility version of the
packages is provided that works great in VHDL-1993, which is the
version of VHDL they were tested under. They also have no dependencies
to the other new VHDL packages.
The compatibility package is synthesizable.
The files on the web page to download are:
Fixed_pkg_c.vhd - Fixed-point package (VHDL-93 compatibility version)
This file should be compiled into a library called ?ieee_proposed?.
-----------------------------------------------------------------------
(I am using Synplify-Pro 8.2)
I followed the instruction and in synplify-Pro i made a project and
added source files :

(1) fixed_generic_pkg.vhd

(2) fixed_generic_pkg_body.vhd

(3) fixed_pkg.vhd


Than from PROJECT --> set VHDL library .

Here I entered the IEEE_proposed in the library names and selet the
absolute radio button.

Now all the source files were displaying ieee_proposed instead of WORK.

When I compile, I get following error:

***********************************************

Synplicity VHDL Compiler, version 3.2.0, Build 069R, built Aug 26 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved

@N:Can't find top module!
Top entity isn't set yet!
@E: CD498
:"C:\DavidFloatingPoint\pkg2\fixed_generic_pkg.vhd":984:22:984:25|Expecting
type name
@E: CD428
:"C:\DavidFloatingPoint\pkg2\fixed_generic_pkg.vhd":1236:29:1236:29|Duplicate
definition of package fixed_generic_pkg
2 errors parsing file C:\DavidFloatingPoint\pkg2\fixed_generic_pkg.vhd
@END
@E: CD498
:"C:\DavidFloatingPoint\pkg2\fixed_generic_pkg_body.vhd":4611:22:4611:25|Expecting
type name
@E: CD415
:"C:\DavidFloatingPoint\pkg2\fixed_generic_pkg_body.vhd":6095:34:6095:34|Expecting
keyword is
4 errors parsing file
C:\DavidFloatingPoint\pkg2\fixed_generic_pkg_body.vhd
@END
@E|Parse errors encountered - exiting

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