IEEE 1076.6 compliance

[cp]

Hi,

Could anyone advise me which synthesis software packages that claim to
be IEEE 1076.6 (VHDL Synthesis Interoperability standard) compliant?

Thank you for your time.

regards,
cp

 

[Mike Treseler]

cp wrote:

Could anyone advise me which synthesis software packages that claim to
be IEEE 1076.6 (VHDL Synthesis Interoperability standard) compliant?

You don't need any special vendor packages for synthesis.
ieee.std_logic_1164 and maybe ieee.numeric_std are all you need.
Successful synthesis has more to do with coding style.

--Mike Treseler

 

[cp]

Mike Treseler <mike_treseler@comcast.net> wrote in message news:<xL-dnVYt4_ZsTL3cRVn-jQ@comcast.com>...

cp wrote:

Could anyone advise me which synthesis software packages that claim to
be IEEE 1076.6 (VHDL Synthesis Interoperability standard) compliant?

You don't need any special vendor packages for synthesis.
ieee.std_logic_1164 and maybe ieee.numeric_std are all you need.
Successful synthesis has more to do with coding style.

--Mike Treseler

Thank you for your prompt response.

My question is about code portability. As its name shows, the 1076.6
is for synthesis interoperability. The interoperability can only be
achieved if this standard is widely adopted by the EDA tool venders.
I am just wondering which vendor makes its synthesis tool compliant
with 1076.6.

regards,
cp

 

[Mike Treseler]

cp wrote

I am just wondering which vendor makes its synthesis tool compliant
with 1076.6.

Most do.
1076.6 is a kind of a minimal common subset of synthesis templates.
It is not a style guide.
http://groups.google.com/groups?q=vhdl+style+synthesis+process+clk

-- Mike Treseler

 

[Eric Delage]

I think that you're still not answering the question ;-)

It's not only a matter of VHDL coding style. If most of the vendors supports
the same IEEE packages (numeric_std and numeric_bit) as defined in 1076.6,
some of them still ignore the standardized syntax for the comments intended
to enable/disable the synthesis process. In 1076.6, they are defined as --
RTL_SYNTHESIS ON and -- RTL_SYNTHESIS OFF but some vendors do not support
them (Synplify Pro from Synplicity for instance (please correct me if I make
a mistake)) and most of the vendors support the "de-facto" Synopsys
comments -- SYNTHESIS TRANSLATE_ON and TRANSLATE_OFF.

As a general comment, I would say that 1076.6 defines a synthesis subset w/o
being 100% clear on corner cases. For instance, you might find some VHDL
parsing problems (my favorites are the support for the correct use of the
VHDL namespaces (thanks to Synplify Pro from Synplicity (note that they are
correcting it)), or the correct support for separate VHDL files (thanks to
XST from Xilinx (no idea whether they have corrected it in the last
version)) which are part of the 1076.1 standard but not mentionned in the
1076.6. Support for 1076.6 would not ensure that you're portable between
synthesizers.

As far as I remember, I never encountered 1076.6 compliancy or VHDL parsing
issues w/ Synopsys/DC-Compiler. But when you consider VHDL synthesis, the
quality of VHDL synthesis results is much more important than portability.
Synopsys and Synplicity are top-level products (if you don't care about
unfortunate bugs that any tool might have). XST is also improving quite
fast.

Eric