M
Mark Curry
Guest
I've got some testbench stuff that's registering design information at time
zero of a sim.
Currently some of this information is the module hier. name. I capture this
into a SystemVerilog string with:
foo_class.set_hier_path( $psprintf( "%m" ) );
I now need a way to capture the module name of the grandparent. (Not the
instance name, the module name). (Take as granted the grandparent module
exists).
It's been a long time since I've delved into the PLI, and am hesitant
to do so, but think I must. There was some link I once followed on
using the SystemVerilog DPI to actually call PLI tasks. I remember
when I saw it thinking "ok neat." It had something to do with
doing a DPI import of a PLI function. But I can't find the link
anymore. At the time I read it, it seemed to be a way of avoiding the
veriuser/tab file/etc mess. Or at least some of the mess.
Any nifty ideas anyone have out there? I've got a nagging feeling there's
some obvious systemtask I'm missing or forgetting. But after mulling
for a while, I can't think of it...
Thanks,
Mark
zero of a sim.
Currently some of this information is the module hier. name. I capture this
into a SystemVerilog string with:
foo_class.set_hier_path( $psprintf( "%m" ) );
I now need a way to capture the module name of the grandparent. (Not the
instance name, the module name). (Take as granted the grandparent module
exists).
It's been a long time since I've delved into the PLI, and am hesitant
to do so, but think I must. There was some link I once followed on
using the SystemVerilog DPI to actually call PLI tasks. I remember
when I saw it thinking "ok neat." It had something to do with
doing a DPI import of a PLI function. But I can't find the link
anymore. At the time I read it, it seemed to be a way of avoiding the
veriuser/tab file/etc mess. Or at least some of the mess.
Any nifty ideas anyone have out there? I've got a nagging feeling there's
some obvious systemtask I'm missing or forgetting. But after mulling
for a while, I can't think of it...
Thanks,
Mark