IDE Ultra DMA on a SPARTAN II

[steven derrien]

Hi folks,

In the context of a research project, we are currently
working on a IDE Hard drive interface targetting the
Spartan-II/Virtex architecture.

On our prototype we simply used PIO mode, but we would
like to extend our controller so that it can handle UDMA.

The problem is that we just realized that this protocol is
somewhat tricky, more specifically we are concerned on how
to implement "source synchronous" aspects of the protocol
expecially for read operation (see below).

_______________ ____________ __________________

\ / \ /
Data ??? X Valid Data X ??????

_______________/ \____________/ \________________

<------------>
5 ns

_________________
DMARdy / \
_______________________/ \________


DMARdy and DATA are both sourced by the hard drive side.

According to the IDE/ATA spec (or at least what I understood
from it) the data should be sampled on a rising edge of
DMA_Rdy.

To us, the most simple solution would be to use the DMARdy
as a clock signal to sample the data in the IOB registers,
then re-synchronize to the FPGA system clock with another
register. However, we are not sure that this is a safe approach
with respect to signal integrity.

Besides, we realized (too late, of course) that the DMARdy
pin of the IDE drive is not connected to a GCK pin ...

Would anybody have somme idea on how to solve this issue ??

Thank you very much in advance.

Steven

 

[noone]

ultra dma? what spec are you refer to? assume you talking about ata6/ultra dma-100 . if its true, dada is clocked by hstrobe or dstrobe during ultra dma, while ddmardy or hdmardy are for control. <p>you may download the spec from t13 web site and digest it, man, they talk alot in there.

 

[steven derrien]

ultra dma? what spec are you refer to? assume you talking about
ata6/ultra dma-100 . if its true, dada is clocked by hstrobe or dstrobe
during ultra dma, while ddmardy or hdmardy are for control.

Sorry, I really should have double checked befor posting.
It is indeed the dstrotre signals that I should have
refered to. I have cancelled my previous message and posted
a more accurate version(I least I hope it is so)

you may download the spec from t13 web site and digest it, man, they
talk alot in there.

I have looked to the spec, but they don't really answer my questions.

Regards

Steven

 

[nomanland]

hi, <BR>
for PIO mode, the DIOR (DDMARDY?) is the data strobe. 20ns setup, 5ns hold time is guaranteed by device. At the host side, if you use spatan or virtex, I believe xilinx FPGA does not required hold time and you have plenty of setup time already. <BR>
For ultra DMA mode, its more tricky. <BR>
Data is strobed by both edges of DSTROBE (DMA in) <p>I believe ATA-6 spec do not recommend to strobe data directly with DSTROBE. Instead using another clock "synchronized version of DSTROBE" (thats what they said : ) to strobe data during DMA in. You may look at 6 asynchronous circuits <BR>
by Petter at xilinx web site for reference, <p>good luck