IDE/ATA _device_ core availablility

[Holger Baxmann]

Hi all,

does anybody know, where, a possibly free, IP core of an IDE _device_
exists?

Reason: connecting a FPGA to an [PC] the standard USB-to-IDE or direct IDE
interface way.

Thanks a lot

bax

 

[Dave Vanden Bout]

"Holger Baxmann" <holger@bitwind.org> wrote in
news:c9pvir$4k6$1@newsreader2.netcologne.de:

Hi all,

does anybody know, where, a possibly free, IP core of an IDE _device_
exists?

Reason: connecting a FPGA to an [PC] the standard USB-to-IDE or direct
IDE interface way.

I've never seen the VHDL for a device-side IDE interface, but it
shouldn't be too hard to do at least a PIO-mode interface. All you need
to do is respond to reads and writes to two banks of eight registers each
and generate the appropriate actions (maybe just read and write sector
commands). I recommend looking at an early version of the ATA spec
(before they got to several hundred pages) to see how the interface
works. The one I've used is "ATA Interface Reference Manual" published
by Seagate back in 1993 (stored at
http://www1.vobis.de/bbs/firmen/seagate/manual/atarevc.pdf)

Once you get a design roughed out, you could combine it in an FPGA or
simulator with the IDE interface core we have at www.xess.com. That
would show you if your device-side interface is alive before subjecting
it to a real-world command stream from a PC IDE port.


----------------------------------------------------------------
Dr. Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com