iCE40 Ultra Family Data Sheet...

[Rick C]

Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with the remaining supplies to be brought up anytime after Vcc/Vccpll. In each case the prior supplies must reach 0.5V before the next supply should be raised.

Then in section 4.6 External Reset, when SPI_V CCIO1 and V PP_2V5 are connected together they are brought up at the same time.

Does anyone understand what is going on with this sequence? When they say A before B, do they really mean A not later than B? I guess it\'s a bit moot. If they aren\'t tied together there is no way to assure A is not later than B other than by making sure A is BEFORE B.

They also have an odd voltage spec on V PP_2V5, up to 3.46V (3.3+5%) unless programming NVCM when only 3.0 is allowed. Needing to drop the voltage for programming is not only odd, but messy. Is NVCM programming typically done on the chip prior to assembly?

I guess the bottom line is that there needs to be two power supplies for this part unless the parts need to have the NV ram configured in which case there needs to be three supplies with appropriate sequencing OR all the non Vcc/Vccpll supplies can be used at 3.0 volts or less.

Very messy.

This is important to me because I need to have a precise supply for one VCCIO so to use outputs and LVDS inputs as comparators in SD ADCs.

Ultimately the accuracy of an ADC will be limited by the VCCIO voltage accuracy unless a reference is measured at the same time and used to calibrate each reading. The sensors being measured have outputs relative to their power supply, so that supply would be measured and divided into each signal measurement taken.

Crap, now I need to decide how to do a division in an FPGA. Newton-Raphson iteration maybe? I think that is what was used in an array processor I worked on many years ago (a floating point processor in a 240 volt powered rack cabinet).

--

Rick C.

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[Michael Kellett]

On 25/08/2020 17:42, Rick C wrote:

Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with the remaining supplies to be brought up anytime after Vcc/Vccpll. In each case the prior supplies must reach 0.5V before the next supply should be raised.

Then in section 4.6 External Reset, when SPI_V CCIO1 and V PP_2V5 are connected together they are brought up at the same time.

Does anyone understand what is going on with this sequence? When they say A before B, do they really mean A not later than B? I guess it\'s a bit moot. If they aren\'t tied together there is no way to assure A is not later than B other than by making sure A is BEFORE B.

They also have an odd voltage spec on V PP_2V5, up to 3.46V (3.3+5%) unless programming NVCM when only 3.0 is allowed. Needing to drop the voltage for programming is not only odd, but messy. Is NVCM programming typically done on the chip prior to assembly?

I guess the bottom line is that there needs to be two power supplies for this part unless the parts need to have the NV ram configured in which case there needs to be three supplies with appropriate sequencing OR all the non Vcc/Vccpll supplies can be used at 3.0 volts or less.

Very messy.

This is important to me because I need to have a precise supply for one VCCIO so to use outputs and LVDS inputs as comparators in SD ADCs.

Ultimately the accuracy of an ADC will be limited by the VCCIO voltage accuracy unless a reference is measured at the same time and used to calibrate each reading. The sensors being measured have outputs relative to their power supply, so that supply would be measured and divided into each signal measurement taken.

Crap, now I need to decide how to do a division in an FPGA. Newton-Raphson iteration maybe? I think that is what was used in an array processor I worked on many years ago (a floating point processor in a 240 volt powered rack cabinet).

I\'ve always followed a hint from a lattice dev board and connected V2.5
to V33 via a diode.
I had a design that used a resistor (idea from different Lattice dev
board) but it worked with a 1k part but not a 4k part.


MK

 

[Gabor]

On Tuesday, 8/25/2020 12:42 PM, Rick C wrote:

Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with the remaining supplies to be brought up anytime after Vcc/Vccpll. In each case the prior supplies must reach 0.5V before the next supply should be raised.

Then in section 4.6 External Reset, when SPI_V CCIO1 and V PP_2V5 are connected together they are brought up at the same time.

Does anyone understand what is going on with this sequence? When they say A before B, do they really mean A not later than B? I guess it\'s a bit moot. If they aren\'t tied together there is no way to assure A is not later than B other than by making sure A is BEFORE B.

They also have an odd voltage spec on V PP_2V5, up to 3.46V (3.3+5%) unless programming NVCM when only 3.0 is allowed. Needing to drop the voltage for programming is not only odd, but messy. Is NVCM programming typically done on the chip prior to assembly?

I guess the bottom line is that there needs to be two power supplies for this part unless the parts need to have the NV ram configured in which case there needs to be three supplies with appropriate sequencing OR all the non Vcc/Vccpll supplies can be used at 3.0 volts or less.

Very messy.

This is important to me because I need to have a precise supply for one VCCIO so to use outputs and LVDS inputs as comparators in SD ADCs.

Ultimately the accuracy of an ADC will be limited by the VCCIO voltage accuracy unless a reference is measured at the same time and used to calibrate each reading. The sensors being measured have outputs relative to their power supply, so that supply would be measured and divided into each signal measurement taken.

Crap, now I need to decide how to do a division in an FPGA. Newton-Raphson iteration maybe? I think that is what was used in an array processor I worked on many years ago (a floating point processor in a 240 volt powered rack cabinet).

I\'ve generally used an LDO per supply for these parts (or a FET switch
to sequence existing voltages that otherwise would not come up in the
correct order). Something like an MCP1725 is nice because it has both
enable input and power good output, so sequencing can be a daisy chain.
The power good of the last supply drives the CRESET_B input of the FPGA.

Also of note, be careful with your IO count. Those RGB pins are not
easily usable for general I/O. If you use an external memory for
program (internal NVM is one-time programmable) you also use up a few
I/O pins for the SPI interface.

Finally I learned the hard way that the PLL in these parts is in an IOB
and restricts the usage of the pin in that IOB if you use the PLL.

Good luck

-- Gabor


--
Gabor

 

[Rick C]

On Thursday, August 27, 2020 at 12:21:37 PM UTC-4, Gabor wrote:

On Tuesday, 8/25/2020 12:42 PM, Rick C wrote:
Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with the remaining supplies to be brought up anytime after Vcc/Vccpll. In each case the prior supplies must reach 0.5V before the next supply should be raised.

Then in section 4.6 External Reset, when SPI_V CCIO1 and V PP_2V5 are connected together they are brought up at the same time.

Does anyone understand what is going on with this sequence? When they say A before B, do they really mean A not later than B? I guess it\'s a bit moot. If they aren\'t tied together there is no way to assure A is not later than B other than by making sure A is BEFORE B.

They also have an odd voltage spec on V PP_2V5, up to 3.46V (3.3+5%) unless programming NVCM when only 3.0 is allowed. Needing to drop the voltage for programming is not only odd, but messy. Is NVCM programming typically done on the chip prior to assembly?

I guess the bottom line is that there needs to be two power supplies for this part unless the parts need to have the NV ram configured in which case there needs to be three supplies with appropriate sequencing OR all the non Vcc/Vccpll supplies can be used at 3.0 volts or less.

Very messy.

This is important to me because I need to have a precise supply for one VCCIO so to use outputs and LVDS inputs as comparators in SD ADCs.

Ultimately the accuracy of an ADC will be limited by the VCCIO voltage accuracy unless a reference is measured at the same time and used to calibrate each reading. The sensors being measured have outputs relative to their power supply, so that supply would be measured and divided into each signal measurement taken.

Crap, now I need to decide how to do a division in an FPGA. Newton-Raphson iteration maybe? I think that is what was used in an array processor I worked on many years ago (a floating point processor in a 240 volt powered rack cabinet).

I\'ve generally used an LDO per supply for these parts (or a FET switch
to sequence existing voltages that otherwise would not come up in the
correct order). Something like an MCP1725 is nice because it has both
enable input and power good output, so sequencing can be a daisy chain.
The power good of the last supply drives the CRESET_B input of the FPGA.

Also of note, be careful with your IO count. Those RGB pins are not
easily usable for general I/O. If you use an external memory for
program (internal NVM is one-time programmable) you also use up a few
I/O pins for the SPI interface.

Finally I learned the hard way that the PLL in these parts is in an IOB
and restricts the usage of the pin in that IOB if you use the PLL.

Thanks for the advice. The possible functionality is increasing and with it the I/O count. lol

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Wednesday, August 26, 2020 at 8:43:54 AM UTC-4, Michael Kellett wrote:

On 25/08/2020 17:42, Rick C wrote:
Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with the remaining supplies to be brought up anytime after Vcc/Vccpll. In each case the prior supplies must reach 0.5V before the next supply should be raised.

Then in section 4.6 External Reset, when SPI_V CCIO1 and V PP_2V5 are connected together they are brought up at the same time.

Does anyone understand what is going on with this sequence? When they say A before B, do they really mean A not later than B? I guess it\'s a bit moot. If they aren\'t tied together there is no way to assure A is not later than B other than by making sure A is BEFORE B.

They also have an odd voltage spec on V PP_2V5, up to 3.46V (3.3+5%) unless programming NVCM when only 3.0 is allowed. Needing to drop the voltage for programming is not only odd, but messy. Is NVCM programming typically done on the chip prior to assembly?

I guess the bottom line is that there needs to be two power supplies for this part unless the parts need to have the NV ram configured in which case there needs to be three supplies with appropriate sequencing OR all the non Vcc/Vccpll supplies can be used at 3.0 volts or less.

Very messy.

This is important to me because I need to have a precise supply for one VCCIO so to use outputs and LVDS inputs as comparators in SD ADCs.

Ultimately the accuracy of an ADC will be limited by the VCCIO voltage accuracy unless a reference is measured at the same time and used to calibrate each reading. The sensors being measured have outputs relative to their power supply, so that supply would be measured and divided into each signal measurement taken.

Crap, now I need to decide how to do a division in an FPGA. Newton-Raphson iteration maybe? I think that is what was used in an array processor I worked on many years ago (a floating point processor in a 240 volt powered rack cabinet).

I\'ve always followed a hint from a lattice dev board and connected V2.5
to V33 via a diode.
I had a design that used a resistor (idea from different Lattice dev
board) but it worked with a 1k part but not a 4k part.


MK

The diode is an interesting idea. Thanks

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

Looks like the iCE40 Ultra parts are out... maybe. Or maybe an even better fit! Seems they don\'t include LVDS inputs! So to implement an ADC requires an external comparator. That sucks, but I/O count is tight and turning LVDS inputs into LVCMOS saves some four or five pins.

Just earlier I found some smaller serial RGB LEDs that save 11 I/O lines making the iCE40 in the QFN48 package a tight fit, now saving 4 more I/Os makes it realistic.

The other alternative is a part from Efinix (new guy on the block) in a 144 QFP!!! Lots of I/Os and a larger logic count with 6 LVDS. Still under $4 qty 100.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Gabor]

On Friday, 8/28/2020 5:21 PM, Rick C wrote:

Looks like the iCE40 Ultra parts are out... maybe. Or maybe an even better fit! Seems they don\'t include LVDS inputs! So to implement an ADC requires an external comparator. That sucks, but I/O count is tight and turning LVDS inputs into LVCMOS saves some four or five pins.

Just earlier I found some smaller serial RGB LEDs that save 11 I/O lines making the iCE40 in the QFN48 package a tight fit, now saving 4 more I/Os makes it realistic.

The other alternative is a part from Efinix (new guy on the block) in a 144 QFP!!! Lots of I/Os and a larger logic count with 6 LVDS. Still under $4 qty 100.

Not sure how you are set for board space, but a 144 TQFP is huge
compared to a 48 QFN.

--
Gabor

 

[Rick C]

On Friday, August 28, 2020 at 6:17:14 PM UTC-4, Gabor wrote:

On Friday, 8/28/2020 5:21 PM, Rick C wrote:
Looks like the iCE40 Ultra parts are out... maybe. Or maybe an even better fit! Seems they don\'t include LVDS inputs! So to implement an ADC requires an external comparator. That sucks, but I/O count is tight and turning LVDS inputs into LVCMOS saves some four or five pins.

Just earlier I found some smaller serial RGB LEDs that save 11 I/O lines making the iCE40 in the QFN48 package a tight fit, now saving 4 more I/Os makes it realistic.

The other alternative is a part from Efinix (new guy on the block) in a 144 QFP!!! Lots of I/Os and a larger logic count with 6 LVDS. Still under $4 qty 100.


Not sure how you are set for board space, but a 144 TQFP is huge
compared to a 48 QFN.

Oh, I know! I\'m not sure how much board space there is either. Rev 1 of the board has room, but we have added a lot of circuitry. Plus there are some hot parts handling power. This was a bit scattered around the board with sensitive circuits near it. I\'m going to try to have it redone with power on one end of the board with the motor controller and the sensitive stuff on the other end of the board. There are no power planes, so the regulators should be near the power entry point and the motor drive near there as well. First routing should be the power runs and everything else will have to squeeze around it. The boards will be made at JLBPCB and I don\'t think they do 2 oz copper, so the power plane heat sinks won\'t be working as well as we might like.

There really aren\'t many options for FPGAs with friendly packages. I\'m really disappointed the Ultras don\'t have LVDS. I thought pretty much every FPGA had them at this point. I\'m also a bit disappointed they don\'t come in bigger packages than 48QFN. A 64QFN with LVDS would solve so many problems.

It\'s ironic that I\'ve been moaning for so long how the world needs a good FPGA in a small non-BGA package and now I need one bigger!

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209