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Just to add - this code has been tested on Modelsim, and alsoWhen I use iverilog for compiling structural verilog code that has no
"always" or "initial" blocks, but only wires and "assign" statements,
I get the error:
invalid module item. Did you forget an initial or always ?
Why is this so?
kb33
When I use iverilog for compiling structural verilog code that has no
"always" or "initial" blocks, but only wires and "assign" statements,
I get the error:
invalid module item. Did you forget an initial or always ?
Why is this so?
kb33
Well, that error message comes with a file/line number. What'sWhen I use iverilog for compiling structural verilog code that has no
"always" or "initial" blocks, but only wires and "assign" statements,
I get the error:
invalid module item. Did you forget an initial or always ?
Why is this so?
You are mis-understanding the error message. It is not sayingThe error is associated with the an output value that has been defined
as a "wire" and is assigned a value using the "assign" command. Error
is also being reported in the following line
(and others similar to it), so I am wondering if defining arrays as
wires is creating a problem.
wire array1 [0:`NUM_NODES-1];
As I had mentioned earlier, this verilog file only has structural
definitions, hence the absence of any "always" or "initial" statement.
It is part of a larger design that has other verilog files with
behavioral descriptions.
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kb33 wrote:
When I use iverilog for compiling structural verilog code that has no
"always" or "initial" blocks, but only wires and "assign" statements,
I get the error:
invalid module item. Did you forget an initial or always ?
Why is this so?
Well, that error message comes with a file/line number. What's
in that line of the file?
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep."
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Yes, I do need an array of scalar nets. I am running the verilog-0.8.5-----BEGIN PGP SIGNED MESSAGE-----
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kb33 wrote:
The error is associated with the an output value that has been defined
as a "wire" and is assigned a value using the "assign" command. Error
is also being reported in the following line
(and others similar to it), so I am wondering if defining arrays as
wires is creating a problem.
wire array1 [0:`NUM_NODES-1];
As I had mentioned earlier, this verilog file only has structural
definitions, hence the absence of any "always" or "initial" statement.
It is part of a larger design that has other verilog files with
behavioral descriptions.
You are mis-understanding the error message. It is not saying
that your code must have "always" or "initial" blocks. It is
saying that the statement it flagged has a syntax error, and it
is suggesting a possible fix.
The line you are showing is an array of scalar nets. Do you really
mean that, or do you want a vector? I'll assume you really do want
an array and not a vector.
In that case, the question is "What version of Icarus Verilog?"
The 0.8 stable releases do not support net arrays. If that is
what you are using, try a recent snapshot.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,http://www.icarus.com and lines to code before I sleep,http://www.picturel.com And lines to code before I sleep."
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I've never found a case where an array of scalar nets would beYes, I do need an array of scalar nets. I am running the verilog-0.8.5
version. This seems to be the latest one.
kb33
When I need a memory array in my design, I have a basic memory blockOn Mar 11, 9:42 am, kb33 <kanchan.devarako...@gmail.com> wrote:
Yes, I do need an array of scalar nets. I am running the verilog-0.8.5
version. This seems to be the latest one.
kb33
I've never found a case where an array of scalar nets would be
required over a vector. Could you elaborate on why a vector wouldn't
work for you?
I appreciate your insights,
- John_H
My intention is to have a clean way of defining memory in my design.
Arrays of nets are usable, certainly, but I still don't see why anMy intention is to have a clean way of defining memory in my design.
When I need a memory array in my design, I have a basic memory block
(such as that described below), and I instantiate it as many times as
the size of the memory array. Hence, I define the array as nets,
because the memory block already has the required registers / vectors
defined. This also avoids the numerous synthesis warnings about not
having the arrays as part of the sensitivity list which I always
happen to get if I use a behavioral approach to defining an array.
Also, I am assuming that defining arrays as nets is not incorrect
because I saw this in one of CLifford Cummings' documents (Verilog
2001 Behavioral and synthesis enhancements).
memory_block #(.DATA_SZ(8)) m0 (.clk(clk),
.reset_n(reset_n),
.mem_we(mem_we),
.mem_enab(me0),
.data_in_bus(data_bus_in0),
.data_out_bus(data_bus_out0)
);
kb33
I have the following sets of code - the input being the same to both.On Mar 11, 11:03 am, kb33 <kanchan.devarako...@gmail.com> wrote:
My intention is to have a clean way of defining memory in my design.
When I need a memory array in my design, I have a basic memory block
(such as that described below), and I instantiate it as many times as
the size of the memory array. Hence, I define the array as nets,
because the memory block already has the required registers / vectors
defined. This also avoids the numerous synthesis warnings about not
having the arrays as part of the sensitivity list which I always
happen to get if I use a behavioral approach to defining an array.
Also, I am assuming that defining arrays as nets is not incorrect
because I saw this in one of CLifford Cummings' documents (Verilog
2001 Behavioral and synthesis enhancements).
memory_block #(.DATA_SZ(8)) m0 (.clk(clk),
.reset_n(reset_n),
.mem_we(mem_we),
.mem_enab(me0),
.data_in_bus(data_bus_in0),
.data_out_bus(data_bus_out0)
);
kb33
Arrays of nets are usable, certainly, but I still don't see why an
array of nets would have function that's different from a vector. If
you're trying to use an array in the memory_block port list, wouldn't
you get an error because Verilog doesn't pass arrays through
modules? ...only vectors and scalars, right?
- John_H
I see nothing particularly wrong with your code.//Second piece of code:
wire [7:0] mem_array[0:3];
wire me0, me1, me2, me3;
assign me0 = (addr == 0) ? 1'b1 : 1'b0;
assign me1 = (addr == 1) ? 1'b1 : 1'b0;
assign me2 = (addr == 2) ? 1'b1 : 1'b0;
assign me3 = (addr == 3) ? 1'b1 : 1'b0;
memory_block #(.DATA_SZ(8)) m0 (.clk(clk),
.reset_n(reset_n),
.mem_we(mem_we),
.mem_enab(me0),
.data_in_bus(data_in),
.data_out_bus(mem_array[0])
);
memory_block #(.DATA_SZ(8)) m1 (.clk(clk),......
memory_block #(.DATA_SZ(8)) m2 (.clk(clk),......
memory_block #(.DATA_SZ(8)) m3 (.clk(clk),......
This second piece is what I was not able to compile using icarus.
Anything particularly wrong with it?
//Combinational logic...
always @(reset_n, data_in, addr, mem_we)
begin
if (~reset_n)
for (j=0; j < 4; j=j+1)
mem_array_comb[j] <= 0;
else if (mem_we)
for (j=0; j < 4; j=j+1)
if (j == addr)
mem_array_comb[j] <= data_in;
else
mem_array_comb[j] <= mem_array[j];
else
for (j=0; j < 4; j=j+1)
mem_array_comb[j] <= mem_array[j];
end
Maybe this will solve the warnings.
If the mem_array has a large number of elements, it is not possible toI think that if in this always block you are using mem_array you
should also put it in the sensitivity list
//Combinational logic...
always @(reset_n, data_in, addr, mem_we)
begin
if (~reset_n)
for (j=0; j < 4; j=j+1)
mem_array_comb[j] <= 0;
else if (mem_we)
for (j=0; j < 4; j=j+1)
if (j == addr)
mem_array_comb[j] <= data_in;
else
mem_array_comb[j] <= mem_array[j];
else
for (j=0; j < 4; j=j+1)
mem_array_comb[j] <= mem_array[j];
end
Maybe this will solve the warnings.
For the second block, I have no clue.