icarus verilog 0.9 bug?

[Uwe Kloß]

hi,

I am exporting a verilog deck from electric for simulation with icarus
verilog.

The design is on transistor level (see example below) and electric
uses the primitives tranif0 and tranif1 for the pmos and nmos
transistors. Timing was not exported by electric but edited in.

Unfortunately icarus seems to ignore the delay specification for the
primitive. Anyone got any hints what's wrong here?

Uwe

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
/* Verilog for cell 'inv{sch}' from library 'fire-sim' */
/* Created on Do Okt 12, 2006 01:45:21 */
/* Last revised on Di Dez 15, 2009 17:01:01 */
/* Written on Mo Jan 25, 2010 01:00:57 by Electric VLSI Design System,
version 8.10 */

module inv(a, y);
input a;
output y;

supply1 vdd;
supply0 gnd;
tranif1 #(5) nmos_0(gnd, y, a);
tranif0 #(5) pmos_0(y, vdd, a);
endmodule /* inv */

 

[Jeremy Bennett]

On Mon, 25 Jan 2010 01:19:56 +0100, Uwe Kloß wrote:

I am exporting a verilog deck from electric for simulation with icarus
verilog.

The design is on transistor level (see example below) and electric uses
the primitives tranif0 and tranif1 for the pmos and nmos transistors.
Timing was not exported by electric but edited in.

Unfortunately icarus seems to ignore the delay specification for the
primitive. Anyone got any hints what's wrong here?

Hi Uwe,

You might need to post this question to the Icarus Verilog developers
mailing list. See http://sourceforge.net/mail/?group_id=149850.

HTH,


Jeremy

 

[Cary R.]

Uwe Kloß wrote:

Unfortunately icarus seems to ignore the delay specification for the
primitive. Anyone got any hints what's wrong here?

Icarus has a bug and is ignoring the delay!

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
/* Verilog for cell 'inv{sch}' from library 'fire-sim' */
/* Created on Do Okt 12, 2006 01:45:21 */
/* Last revised on Di Dez 15, 2009 17:01:01 */
/* Written on Mo Jan 25, 2010 01:00:57 by Electric VLSI Design System,
version 8.10 */

module inv(a, y);
input a;
output y;

supply1 vdd;
supply0 gnd;
tranif1 #(5) nmos_0(gnd, y, a);
tranif0 #(5) pmos_0(y, vdd, a);
endmodule /* inv */

There are a couple ways you can make this work. Delay the 'a' signal by
5 instead of the individual tranif statements. Switching the tranif
devices for nmos/pmos also appears to work correctly.

Cary

 

[Uwe Kloß]

Cary R. schrieb:

Uwe Kloß wrote:

Unfortunately icarus seems to ignore the delay specification for the
primitive. Anyone got any hints what's wrong here?

Icarus has a bug and is ignoring the delay!
I thought so, thanks for the confirmation.

Do you have any information on release cycles/time to fix?
I'm new to icarus.

module inv(a, y);
input a;
output y;

supply1 vdd;
supply0 gnd;
tranif1 #(5) nmos_0(gnd, y, a);
tranif0 #(5) pmos_0(y, vdd, a);
endmodule /* inv */

There are a couple ways you can make this work. Delay the 'a' signal by
5 instead of the individual tranif statements.
It is not that simple. I don't design in verilog. I just tried to use it

for simulation because the builtin simulators of electric don't handle
busses very nicely. The verilog source is automatically generated from
schematic/layout (unfortunately without timing info) and the modules are
much more complex than the given inverter. Just delaying the inputs
won't do.

Switching the tranif
devices for nmos/pmos also appears to work correctly.
Yes, but this poses also the problem of port assignment as pmos/nmos are

unidirectional. As you can see in the example above, the exporter is not
very smart when considering signal direction. That's probably the
reason for using tranif: less analysis work. That can easily get very
messy with more complex circuits (e.g. adders).

The insertion of the delay after the tranif is easily done by e.g. m4 or
awk or perl, but your suggestions would mean rework by hand wich I'd
like to avoid.

Perhaps I'll try cver or veriwell as an alternative first.

Uwe

P.S.: I found the there's version 0.9.2 out. I'll check that one first.

 

[Cary R.]

Uwe Kloß wrote:

I thought so, thanks for the confirmation.
Do you have any information on release cycles/time to fix?

It depends on the free time the developers have available, but you won't
know until it gets reported. I can easily do that if you don't want to.

Yes, but this poses also the problem of port assignment as pmos/nmos are
unidirectional.

Correct. It sounds like tranif is what you need.

The insertion of the delay after the tranif is easily done by e.g. m4 or
awk or perl, but your suggestions would mean rework by hand wich I'd
like to avoid.

Understood.

Perhaps I'll try cver or veriwell as an alternative first.

I have a simple version of your example with a driver and it doesn't
work at all on Cver (the output is always 'bx). Veriwell appears to work
correctly and may work for what you need.

P.S.: I found the there's version 0.9.2 out. I'll check that one first.

That won't work either. This is not fixed in the latest development
version. Given what needs to be changed it is unlikely this would be
added to the V0.9 branch.

Cary

 

[Uwe Kloß]

Cary R. schrieb:

Uwe Kloß wrote:

I thought so, thanks for the confirmation.
Do you have any information on release cycles/time to fix?

It depends on the free time the developers have available, but you won't
know until it gets reported. I can easily do that if you don't want to.

I saw you went ahead and reported it.
Thanks for that.

Now lets just hope the maintainer(s) win a lottery or get a paid
vacation from their boss. ;-)

Uwe