ic Design

[dude]

I've been trying to look up IC design and can't quite find what i'm looking
for.

I want to know what the shapes look like for transistors and such when they
are drawn in preparation for being transferred to silicon.

I found one site that showed a cell design:

http://www.intel.com/technology/itj/q12001/articles/art_1f.htm

But this doesn't show the individual components. I know this stuff isn't
done by hand anymore but I'd really like to see the shapes of each
component. Can anyone point me in the right direction here?

Thank you...

 

[jw]

http://www.staticfreesoft.com/

check it out.

 

[Jim Thompson]

On Sat, 14 Aug 2004 03:25:34 -0500, "dude" <dast7777@hotmail.com>
wrote:

I've been trying to look up IC design and can't quite find what i'm looking
for.

I want to know what the shapes look like for transistors and such when they
are drawn in preparation for being transferred to silicon.

I found one site that showed a cell design:

http://www.intel.com/technology/itj/q12001/articles/art_1f.htm

But this doesn't show the individual components. I know this stuff isn't
done by hand anymore but I'd really like to see the shapes of each
component. Can anyone point me in the right direction here?

Thank you...

An NMOS device is posted here.......

http://www.analog-innovations.com/SED/NMOS.gif

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[dude]

"Jim Thompson" <thegreatone@example.com> wrote in message
news:it4vh055g5cids3s95s91oklecj0ob3ufs@4ax.com...

On Sat, 14 Aug 2004 03:25:34 -0500, "dude" <dast7777@hotmail.com
wrote:

I've been trying to look up IC design and can't quite find what i'm
looking
for.

I want to know what the shapes look like for transistors and such when
they
are drawn in preparation for being transferred to silicon.

I found one site that showed a cell design:

http://www.intel.com/technology/itj/q12001/articles/art_1f.htm

But this doesn't show the individual components. I know this stuff isn't
done by hand anymore but I'd really like to see the shapes of each
component. Can anyone point me in the right direction here?

Thank you...


An NMOS device is posted here.......

http://www.analog-innovations.com/SED/NMOS.gif

so that is the actuall image that would be imprinted on silicon? if so, that
would suck to have to draw those lines by hand, good thing for CAD....

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Jim Thompson]

On Sun, 15 Aug 2004 21:35:26 -0500, "dude" <dast7777@hotmail.com>
wrote:

"Jim Thompson" <thegreatone@example.com> wrote in message
news:it4vh055g5cids3s95s91oklecj0ob3ufs@4ax.com...
[snip]
An NMOS device is posted here.......

http://www.analog-innovations.com/SED/NMOS.gif


so that is the actuall image that would be imprinted on silicon? if so, that
would suck to have to draw those lines by hand, good thing for CAD....


[snip]

Most are plunked down as a "cell", where all the layers are included
in one "plunk" ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Robert]

"Jim Thompson" <thegreatone@example.com> wrote in message
news:it4vh055g5cids3s95s91oklecj0ob3ufs@4ax.com...
[snip]
An NMOS device is posted here.......

http://www.analog-innovations.com/SED/NMOS.gif


so that is the actuall image that would be imprinted on silicon? if so,
that
would suck to have to draw those lines by hand, good thing for CAD....


[snip]

Most are plunked down as a "cell", where all the layers are included
in one "plunk" ;-)

And even simple Layout editors allow you to grab sides of the cell and
stretch them to fit your application if the Foundry allows such. The
stretching keeps all layers in alignment if you do it right. So you can make
one cell fit different applications.

This place has a demo version of their layout editor with a tutorial that
might show you some of the transistor layouts.

http://www.iceditors.com/support/public/demo.html

 

[dude]

OK, so who figured out that these shapes would do the things that they do?
Like being a transistor? It seems so strange. It is also very hard to find
the exact info I'm looking for on the web. Know any book title that get down
to this level?

Or do you know of any website that just shows the pictures of all these
components.

Another question, are there any kits out there that let you design a really
basic IC? That would be cool....



"Robert" <robert@yahoo.com> wrote in message
news:RurUc.3933$3O3.3707@newsread2.news.pas.earthlink.net...

"Jim Thompson" <thegreatone@example.com> wrote in message
news:it4vh055g5cids3s95s91oklecj0ob3ufs@4ax.com...
[snip]
An NMOS device is posted here.......

http://www.analog-innovations.com/SED/NMOS.gif


so that is the actuall image that would be imprinted on silicon? if so,
that
would suck to have to draw those lines by hand, good thing for CAD....


[snip]

Most are plunked down as a "cell", where all the layers are included
in one "plunk" ;-)

And even simple Layout editors allow you to grab sides of the cell and
stretch them to fit your application if the Foundry allows such. The
stretching keeps all layers in alignment if you do it right. So you can
make
one cell fit different applications.

This place has a demo version of their layout editor with a tutorial that
might show you some of the transistor layouts.

http://www.iceditors.com/support/public/demo.html

 

[Robert]

They figured out the transistor from Sold State Physics.

The way we make transistors today isn't how they used to do it (look up
"Alloy" or "Mesa Transistors" sometime).

There are several different types of Transistors. Look up "Bipolar", "Jfet",
and "Mosfet" sometime. There are others.

You can design a circuit using transistors, resistors, and capacitors in any
Spice simulator. Or rather, you can design the circuit and have Spice
simulate how it would perform. Then you can take that circuit and put in on
an IC. They have similar components available.

With the tool I posted, or others, you can make the physical circuit on the
IC by selecting components from Libraries.

Standard texts, like Gray and Meyer, have sections on the circuits, as well
as a chapter on how the circuits are made on IC chips.

But I've always like "The Art of Electronics" for more of a well rounded
resource for beginners.

Robert


"dude" <dast7777@hotmail.com> wrote in message
news:10i8qc4p366igcf@corp.supernews.com...

OK, so who figured out that these shapes would do the things that they do?
Like being a transistor? It seems so strange. It is also very hard to find
the exact info I'm looking for on the web. Know any book title that get
down
to this level?

Or do you know of any website that just shows the pictures of all these
components.

Another question, are there any kits out there that let you design a
really
basic IC? That would be cool....

 

[Vincent Himpe]

"dude" <dast7777@hotmail.com> wrote in
news:10hrj3vgn2idcf2@corp.supernews.com:

I've been trying to look up IC design and can't quite find what i'm
looking for.

I want to know what the shapes look like for transistors and such when
they are drawn in preparation for being transferred to silicon.

I found one site that showed a cell design:

http://www.intel.com/technology/itj/q12001/articles/art_1f.htm

But this doesn't show the individual components. I know this stuff
isn't done by hand anymore but I'd really like to see the shapes of
each component. Can anyone point me in the right direction here?

Thank you...

There are a couple of books out there that explain how it's done.

H.M.Veendrick has a good book on MOS design.

Problem with IC design is that it is not portable. You ned to know the
proecess technology you want to design in before you start. The layer
stack needs to be know, how many poly layers you have , how many oxides ,
nitrides , metal layers , geometries , and a whole bunch of electrical
properties.
Then you can design your primitives like resistors, transistors etc. All
of that is more material physics then electronics.

For instance a resistor. A resistor is specified in units. lets say 1
square micron is a unit. ( were are not talking in ohms here ! )
If you want to double the value you put two next to each other. you have
now a resistor 2 micron long and 1 micron wide. Triple the value : 3
micron long and 1 micron wide.

The curent needs to be higher trough the rsistor : double the width to 2
micron and make it 6 micron long.

For a certain technology the spec might read 1 unit is approx 1 kilohm ,
but it can drift from 800 ohm to 2 kilohm depending on prcess shift.
Silicon design is not so much about absolute values but more about
ratio's.

Transistor design :

A MOs is basically a 'well' ( Doped region inside the silicon ) The gate
i a piece of Poly that lies over this 'well'. THe widh of the gate
detemines the voltage that it can withstand , the length the amount of
current it can conduct ( in very simple terms ) There are a lot of other
factors , the longer or wider the gate the slower it gets ( the gate is a
capacitor that needs to be 'charged' or 'discharged' also charge
distribution is a problem. If you were to inject charge form one end of
the gate it will take a while for this chare to reach the other end of
the gate. So one end would turn on faster then the other.

Therefore in power transistors you find a metal track running over the
gate that drills down with via's. Metal is much more conductive then poly
silicon

Metal in chips is alminum ( sometimes copper for really expensive stuff )
There can be up to 6 layers ( think of a multilayer PCB )

As for software ; Cadence , Magma , Dracula , Mentor , Eldo ,
AnalogArtist, Avanti and many more : all multi million dollar tools
running on multi million dollar computers (mostly Sun).There is a
migration to Linux

For a place and route ( think of a board autoroute ) we use Sun servers
with 16 CPU's each having up to 24 Gig's of ram per CPU. We are
experimenting with linux 'compute farms' put 50 or so PIV 3 GHZ with 2 to
4 Gig of ram each in an array and run.

A typical place and route is human assisted ( full autorouting does not
exist ) and can take up to 3 months with 4 people and 2 of those
computers.

Layout is done block per block and . After the layout is done , timing
and capacitance information is extracted and the dsign checked to see if
all signals will arrive at the correct time. Contrary to popular belief
there is a finite amount of time to send a signal from point A to B on a
chip. This depends on stray capacitance , curent used etc. In a digital
chip there are a lot of 'near analog' signal amplifiers along the way
from point A to B, fortunately we have tools today that are smart enough
to insert where necessary. The problem is that the signal is delayed evry
ime i goues trough an amplifier. So if you need to 'AND' two signals ,
one local and one that needs to come from the other end of the chip and
needs to pass 20 amplifiers you have to account for that time difference.
in the loal signal delays will b inserted ( we have delay generators to
insert )

Tha's where the humans come in . They check , simulte and recheck with
the dsigner. Once a block is clean and all outputs are synchronised in
time they move on to the next cell.

Eventually all blocks are places and the interconnection routing is
placed.
Then the io pads are put in place , ESD protection cells etc.
Finally the computer produce a 'tape out' ( historycally this was on 9600
bit per inch tape like you see in old science fiction movies, actually
this was still in use up til 1995. Today we use either MO or DLT. A large
design can be 10 to 15 tapes that hold each 40 Gigs of data )

This tap out has many generated layers ( isolation masks etc ) A chip in
a waferfab can require up to 150 proces steps. ( some go to 300 steps )
and require 20 or 30 'masks'. a mask is a negative that holds the
information for one layer.

A maskset's price increases with the smallness of the geometies. And its
exponential. Maskset for a 0.5 micron technology : arund 1 Mo $
Makset for 0.25 : around 3 MO$ . Maskset for 0.13 micron : 12 Mo $

If you really want to expeiment there is one option ( completely free )

http://members.aol.com/lasicad/

THis is a chip desing tool written by ex- or retired employees of Texas
instruemtns and some big US universities. It is completely freeware ,
works pretty well ( not for large designs ). I've toyed with it a couple
of times and it can even open the output we generate albeit slow.

Hope this satisfies your curiosity a bit.

Keep in mind that a lot what i said in this thing is oversimplified.There
are many more factors to be acocounted for.
I've been working in chip design for 15 years (First alcatel now ST
micro)